文件名称:uart_verilog
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- 上传时间：2012-11-16
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文件大小：4.75kb
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The UART design was designed from a standard uart function with a read/write microprocessor interface. It includes standard framing error, parity control and overrun detection.
This design is targeted to the XCR3128XL-7VQ100C CoolRunner CPLD. This is a 3V, 128 macrocell device in a 100 VQFP package. The fitter was allowed to pick the pin-out for the device.
-The UART design was designed from a standard uart function with a read/write microprocessor interface. It includes standard framing error, parity control and overrun detection.
This design is targeted to the XCR3128XL-7VQ100C CoolRunner CPLD. This is a 3V, 128 macrocell device in a 100 VQFP package. The fitter was allowed to pick the pin-out for the device.
This design is targeted to the XCR3128XL-7VQ100C CoolRunner CPLD. This is a 3V, 128 macrocell device in a 100 VQFP package. The fitter was allowed to pick the pin-out for the device.
-The UART design was designed from a standard uart function with a read/write microprocessor interface. It includes standard framing error, parity control and overrun detection.
This design is targeted to the XCR3128XL-7VQ100C CoolRunner CPLD. This is a 3V, 128 macrocell device in a 100 VQFP package. The fitter was allowed to pick the pin-out for the device.
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下载文件列表
uart_verilog/rcvr.v
uart_verilog/rcvr_tf.v
uart_verilog/readme.txt
uart_verilog/txmit.v
uart_verilog/txmit_tf.v
uart_verilog/uart.v
uart_verilog/
uart_verilog/rcvr_tf.v
uart_verilog/readme.txt
uart_verilog/txmit.v
uart_verilog/txmit_tf.v
uart_verilog/uart.v
uart_verilog/
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