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文件名称:booth_multiplier

  • 所属分类：
    VHDL-FPGA-Verilog
  • 标签属性：
    [Windows] [程序]
  • 上传时间：
    2012-11-16
  • 文件大小：
    10.96mb
  • 已下载：
    0次
  • 提 供 者：
    K*****
  • 相关连接：
    无
  • 下载说明：
    别用迅雷下载，失败请重下，重下不扣分！
修正介绍说明

介绍说明－－下载内容来自于网络，使用问题请自行百度

This source code makes 8 X 8 booth multiplier and it is coded in Velilog HDL.
(系统自动生成,下载前可以参看下载内容)

下载文件列表

berwer/.simvision/dbrowser-bookmarks
berwer/.simvision/schematic-bookmarks
berwer/.simvision/source-bookmarks
berwer/INCA_libs/worklib/.cdsvmod
berwer/INCA_libs/worklib/.inca.db.165.sun4v
berwer/INCA_libs/worklib/inca.sun4v.165.pak
berwer/hdl/TB_Booth_Mul_8x8.v
berwer/hdl/booth_multiplier.v
berwer/waves.shm/waves-1.trn
berwer/waves.shm/waves-2.trn
berwer/waves.shm/waves.dsn
berwer/waves.shm/waves.trn
berwer/.nclaunch.dd
berwer/booth_2009307045_RCA.dsn
berwer/booth_2009307045_RCA.trn
berwer/cds.lib
berwer/hdl.var
berwer/ncelab.log
berwer/nclaunch.key
berwer/ncsim.key
berwer/ncsim.log
berwer/ncvlog.log
berwer/out.dat
berwer2/hdl/TB_Booth_Mul_8x8.v
berwer2/hdl/TB_Booth_Mul_8x8.v~
berwer2/hdl/booth_multiplier.v
berwer2/hdl/booth_multiplier.v~
berwer2/lib/work/ADDER_TREE.mr
berwer2/lib/work/BOOTH_2009307045.mr
berwer2/lib/work/CARRY_LA_GEN.mr
berwer2/lib/work/COMPRESSOR4_2.mr
berwer2/lib/work/Carry_LA_Gen-verilog-verilog.syn
berwer2/lib/work/Carry_LA_Gen-verilog.pvl
berwer2/lib/work/Carry_LA_Gen-verilog.syn
berwer2/lib/work/FULL_ADDER.mr
berwer2/lib/work/HALF_ADDER.mr
berwer2/lib/work/INPUT_BUFFER.mr
berwer2/lib/work/LOOKAHEAD.mr
berwer2/lib/work/LOOKAHEAD_4.mr
berwer2/lib/work/LOOKAHEAD_4_MSB.mr
berwer2/lib/work/PARTIAL_PRODUCT_GENERATOR.mr
berwer2/lib/work/adder_tree-verilog-verilog.syn
berwer2/lib/work/adder_tree-verilog.pvl
berwer2/lib/work/adder_tree-verilog.syn
berwer2/lib/work/booth_2009307045-verilog-verilog.syn
berwer2/lib/work/booth_2009307045-verilog.pvl
berwer2/lib/work/booth_2009307045-verilog.syn
berwer2/lib/work/compressor4_2-verilog-verilog.syn
berwer2/lib/work/compressor4_2-verilog.pvl
berwer2/lib/work/compressor4_2-verilog.syn
berwer2/lib/work/full_adder-verilog-verilog.syn
berwer2/lib/work/full_adder-verilog.pvl
berwer2/lib/work/full_adder-verilog.syn
berwer2/lib/work/half_adder-verilog-verilog.syn
berwer2/lib/work/half_adder-verilog.pvl
berwer2/lib/work/half_adder-verilog.syn
berwer2/lib/work/input_buffer-verilog-verilog.syn
berwer2/lib/work/input_buffer-verilog.pvl
berwer2/lib/work/input_buffer-verilog.syn
berwer2/lib/work/lookahead-verilog-verilog.syn
berwer2/lib/work/lookahead-verilog.pvl
berwer2/lib/work/lookahead-verilog.syn
berwer2/lib/work/lookahead_4-verilog-verilog.syn
berwer2/lib/work/lookahead_4-verilog.pvl
berwer2/lib/work/lookahead_4-verilog.syn
berwer2/lib/work/lookahead_4_msb-verilog-verilog.syn
berwer2/lib/work/lookahead_4_msb-verilog.pvl
berwer2/lib/work/lookahead_4_msb-verilog.syn
berwer2/lib/work/partial_product_generator-verilog-verilog.syn
berwer2/lib/work/partial_product_generator-verilog.pvl
berwer2/lib/work/partial_product_generator-verilog.syn
berwer2/lib/ci025a.sdb
berwer2/lib/ci025a_02.db
berwer2/log/command.log
berwer2/log/filename.log
berwer2/mapped/
berwer2/netlist/
berwer2/report/
berwer2/script/booth_read.scr
berwer2/script/booth_read.scr~
berwer2/script/booth_syn.scr
berwer2/script/booth_syn.scr~
berwer2/sdc/
berwer2/unmapped/
berwer2/.synopsys_dc.setup
booth/.simvision/dbrowser-bookmarks
booth/.simvision/schematic-bookmarks
booth/.simvision/source-bookmarks
booth/INCA_libs/worklib/.cdsvmod
booth/INCA_libs/worklib/.inca.db.165.sun4v
booth/INCA_libs/worklib/inca.sun4v.165.pak
booth/hdl/TB_Booth_Mul_8x8.v
booth/hdl/booth_multiplier.v
booth/hdl/booth_multiplier.v~
booth/lib/work/ADDER_TREE.mr
booth/lib/work/BOOTH_2009307045.mr
booth/lib/work/CARRY_LA_GEN.mr
booth/lib/work/COMPRESSOR4_2.mr
booth/lib/work/Carry_LA_Gen-verilog-verilog.syn
booth/lib/work/Carry_LA_Gen-verilog.pvl
booth/lib/work/Carry_LA_Gen-verilog.syn
booth/lib/work/FULL_ADDER.mr
booth/lib/work/HALF_ADDER.mr
booth/lib/work/INPUT_BUFFER.mr
booth/lib/work/LOOKAHEAD.mr
booth/lib/work/LOOKAHEAD_4.mr
booth/lib/work/LOOKAHEAD_4_MSB.mr
booth/lib/work/PARTIAL_PRODUCT_GENERATOR.mr
booth/lib/work/adder_tree-verilog-verilog.syn
booth/lib/work/adder_tree-verilog.pvl
booth/lib/work/adder_tree-verilog.syn
booth/lib/work/booth_2009307045-verilog-verilog.syn
booth/lib/work/booth_2009307045-verilog.pvl
booth/lib/work/booth_2009307045-verilog.syn
booth/lib/work/compressor4_2-verilog-verilog.syn
booth/lib/work/compressor4_2-verilog.pvl
booth/lib/work/compressor4_2-verilog.syn
booth/lib/work/full_adder-verilog-verilog.syn
booth/lib/work/full_adder-verilog.pvl
booth/lib/work/full_adder-verilog.syn
booth/lib/work/half_adder-verilog-verilog.syn
booth/lib/work/half_adder-verilog.pvl
booth/lib/work/half_adder-verilog.syn
booth/lib/work/input_buffer-verilog-verilog.syn
booth/lib/work/input_buffer-verilog.pvl
booth/lib/work/input_buffer-verilog.syn
booth/lib/work/lookahead-verilog-verilog.syn
booth/lib/work/lookahead-verilog.pvl
booth/lib/work/lookahead-verilog.syn
booth/lib/work/lookahead_4-verilog-verilog.syn
booth/lib/work/lookahead_4-verilog.pvl
booth/lib/work/lookahead_4-verilog.syn
booth/lib/work/lookahead_4_msb-verilog-verilog.syn
booth/lib/work/lookahead_4_msb-verilog.pvl
booth/lib/work/lookahead_4_msb-verilog.syn
booth/lib/work/partial_product_generator-verilog-verilog.syn
booth/lib/work/partial_product_generator-verilog.pvl
booth/lib/work/partial_product_generator-verilog.syn
booth/lib/ci025a.sdb
booth/lib/ci025a_02.db
booth/log/comma

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