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文件名称:Verilog-Experiment

  • 所属分类：
    VHDL-FPGA-Verilog
  • 标签属性：
    [HTML]
  • 上传时间：
    2012-11-16
  • 文件大小：
    43.88mb
  • 已下载：
    0次
  • 提 供 者：
    李***
  • 相关连接：
    无
  • 下载说明：
    别用迅雷下载，失败请重下，重下不扣分！
修正介绍说明

介绍说明－－下载内容来自于网络，使用问题请自行百度

FPGA开发板Verilog源程序，十分值值学习！

-FPGA Development Board Verilog source program, great value!
(系统自动生成,下载前可以参看下载内容)

下载文件列表

Verilog Experiment/Experiment/Experiment01/db/altsyncram_g204.tdf
Verilog Experiment/Experiment/Experiment01/db/altsyncram_ivv3.tdf
Verilog Experiment/Experiment/Experiment01/db/altsyncram_mdq1.tdf
Verilog Experiment/Experiment/Experiment01/db/cmpr_5cc.tdf
Verilog Experiment/Experiment/Experiment01/db/cmpr_8cc.tdf
Verilog Experiment/Experiment/Experiment01/db/cmpr_9cc.tdf
Verilog Experiment/Experiment/Experiment01/db/cntr_02j.tdf
Verilog Experiment/Experiment/Experiment01/db/cntr_45j.tdf
Verilog Experiment/Experiment/Experiment01/db/cntr_8ai.tdf
Verilog Experiment/Experiment/Experiment01/db/cntr_gui.tdf
Verilog Experiment/Experiment/Experiment01/db/cntr_sbi.tdf
Verilog Experiment/Experiment/Experiment01/db/cntr_ubi.tdf
Verilog Experiment/Experiment/Experiment01/db/decode_rqf.tdf
Verilog Experiment/Experiment/Experiment01/db/led0_module.(0).cnf.cdb
Verilog Experiment/Experiment/Experiment01/db/led0_module.(0).cnf.hdb
Verilog Experiment/Experiment/Experiment01/db/led0_module.amm.cdb
Verilog Experiment/Experiment/Experiment01/db/led0_module.asm.qmsg
Verilog Experiment/Experiment/Experiment01/db/led0_module.asm.rdb
Verilog Experiment/Experiment/Experiment01/db/led0_module.asm_labs.ddb
Verilog Experiment/Experiment/Experiment01/db/led0_module.cbx.xml
Verilog Experiment/Experiment/Experiment01/db/led0_module.cmp.bpm
Verilog Experiment/Experiment/Experiment01/db/led0_module.cmp.cbp
Verilog Experiment/Experiment/Experiment01/db/led0_module.cmp.cdb
Verilog Experiment/Experiment/Experiment01/db/led0_module.cmp.hdb
Verilog Experiment/Experiment/Experiment01/db/led0_module.cmp.kpt
Verilog Experiment/Experiment/Experiment01/db/led0_module.cmp.logdb
Verilog Experiment/Experiment/Experiment01/db/led0_module.cmp.rdb
Verilog Experiment/Experiment/Experiment01/db/led0_module.cmp.tdb
Verilog Experiment/Experiment/Experiment01/db/led0_module.cmp0.ddb
Verilog Experiment/Experiment/Experiment01/db/led0_module.cmp2.ddb
Verilog Experiment/Experiment/Experiment01/db/led0_module.cmp_merge.kpt
Verilog Experiment/Experiment/Experiment01/db/led0_module.db_info
Verilog Experiment/Experiment/Experiment01/db/led0_module.eda.qmsg
Verilog Experiment/Experiment/Experiment01/db/led0_module.fit.qmsg
Verilog Experiment/Experiment/Experiment01/db/led0_module.hier_info
Verilog Experiment/Experiment/Experiment01/db/led0_module.hif
Verilog Experiment/Experiment/Experiment01/db/led0_module.idb.cdb
Verilog Experiment/Experiment/Experiment01/db/led0_module.lpc.html
Verilog Experiment/Experiment/Experiment01/db/led0_module.lpc.rdb
Verilog Experiment/Experiment/Experiment01/db/led0_module.lpc.txt
Verilog Experiment/Experiment/Experiment01/db/led0_module.map.bpm
Verilog Experiment/Experiment/Experiment01/db/led0_module.map.cbp
Verilog Experiment/Experiment/Experiment01/db/led0_module.map.cdb
Verilog Experiment/Experiment/Experiment01/db/led0_module.map.hdb
Verilog Experiment/Experiment/Experiment01/db/led0_module.map.kpt
Verilog Experiment/Experiment/Experiment01/db/led0_module.map.logdb
Verilog Experiment/Experiment/Experiment01/db/led0_module.map.qmsg
Verilog Experiment/Experiment/Experiment01/db/led0_module.map_bb.cdb
Verilog Experiment/Experiment/Experiment01/db/led0_module.map_bb.hdb
Verilog Experiment/Experiment/Experiment01/db/led0_module.map_bb.logdb
Verilog Experiment/Experiment/Experiment01/db/led0_module.pre_map.cdb
Verilog Experiment/Experiment/Experiment01/db/led0_module.pre_map.hdb
Verilog Experiment/Experiment/Experiment01/db/led0_module.rtlv.hdb
Verilog Experiment/Experiment/Experiment01/db/led0_module.rtlv_sg.cdb
Verilog Experiment/Experiment/Experiment01/db/led0_module.rtlv_sg_swap.cdb
Verilog Experiment/Experiment/Experiment01/db/led0_module.sgdiff.cdb
Verilog Experiment/Experiment/Experiment01/db/led0_module.sgdiff.hdb
Verilog Experiment/Experiment/Experiment01/db/led0_module.sld_design_entry.sci
Verilog Experiment/Experiment/Experiment01/db/led0_module.sld_design_entry_dsc.sci
Verilog Experiment/Experiment/Experiment01/db/led0_module.smart_action.txt
Verilog Experiment/Experiment/Experiment01/db/led0_module.syn_hier_info
Verilog Experiment/Experiment/Experiment01/db/led0_module.tan.qmsg
Verilog Experiment/Experiment/Experiment01/db/led0_module.tis_db_list.ddb
Verilog Experiment/Experiment/Experiment01/db/logic_util_heursitic.dat
Verilog Experiment/Experiment/Experiment01/db/mux_aoc.tdf
Verilog Experiment/Experiment/Experiment01/db/mux_boc.tdf
Verilog Experiment/Experiment/Experiment01/db/prev_cmp_led0_module.asm.qmsg
Verilog Experiment/Experiment/Experiment01/db/prev_cmp_led0_module.eda.qmsg
Verilog Experiment/Experiment/Experiment01/db/prev_cmp_led0_module.fit.qmsg
Verilog Experiment/Experiment/Experiment01/db/prev_cmp_led0_module.map.qmsg
Verilog Experiment/Experiment/Experiment01/db/prev_cmp_led0_module.qmsg
Verilog Experiment/Experiment/Experiment01/db/prev_cmp_led0_module.tan.qmsg
Verilog Experiment/Experiment/Experiment01/db/prev_cmp_top_module.qmsg
Verilog Experiment/Experiment/Experiment01/db/top_module.(0).cnf.cdb
Verilog Experiment/Experiment/Experiment01/db/top_module.(0).cnf.hdb
Verilog Experiment/Experiment/Experiment01/db/top_module.(1).

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