文件名称:comp
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- 上传时间:2012-11-16
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verilog FPGA060 比较器实验例程和文档-verilog FPGA060 comparator test routines and documentation
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下载文件列表
comp/comp.prj
comp/designer/impl1/comp.adb
comp/designer/impl1/comp.dat
comp/designer/impl1/comp.dtf/verify.log
comp/designer/impl1/comp.ide_des
comp/designer/impl1/comp.tcl
comp/designer/impl1/designer.log
comp/hdl/comp.v
comp/simulation/modelsim.ini
comp/smartgen/smartgen.aws
comp/synthesis/.recordref
comp/synthesis/comp.areasrr
comp/synthesis/comp.edn
comp/synthesis/comp.map
comp/synthesis/comp.pdc
comp/synthesis/comp.sdf
comp/synthesis/comp.so
comp/synthesis/comp.srd
comp/synthesis/comp.srm
comp/synthesis/comp.srr
comp/synthesis/comp.srs
comp/synthesis/comp.szr
comp/synthesis/comp.tlg
comp/synthesis/comp_sdc.sdc
comp/synthesis/comp_syn.prj
comp/synthesis/run_options.txt
comp/synthesis/stdout.log
comp/synthesis/syntmp/comp.plg
comp/synthesis/traplog.tlg
comp/viewdraw/vf/project.lst
comp/viewdraw/viewdraw.ini
comp/designer/impl1/comp.dtf
comp/designer/impl1/simulation
comp/designer/impl1
comp/synthesis/backup
comp/synthesis/coreip
comp/synthesis/syntmp
comp/viewdraw/sch
comp/viewdraw/sym
comp/viewdraw/vf
comp/viewdraw/wir
comp/component
comp/constraint
comp/coreconsole
comp/designer
comp/hdl
comp/phy_synthesis
comp/simulation
comp/smartgen
comp/stimulus
comp/synthesis
comp/viewdraw
comp
comp/designer/impl1/comp.adb
comp/designer/impl1/comp.dat
comp/designer/impl1/comp.dtf/verify.log
comp/designer/impl1/comp.ide_des
comp/designer/impl1/comp.tcl
comp/designer/impl1/designer.log
comp/hdl/comp.v
comp/simulation/modelsim.ini
comp/smartgen/smartgen.aws
comp/synthesis/.recordref
comp/synthesis/comp.areasrr
comp/synthesis/comp.edn
comp/synthesis/comp.map
comp/synthesis/comp.pdc
comp/synthesis/comp.sdf
comp/synthesis/comp.so
comp/synthesis/comp.srd
comp/synthesis/comp.srm
comp/synthesis/comp.srr
comp/synthesis/comp.srs
comp/synthesis/comp.szr
comp/synthesis/comp.tlg
comp/synthesis/comp_sdc.sdc
comp/synthesis/comp_syn.prj
comp/synthesis/run_options.txt
comp/synthesis/stdout.log
comp/synthesis/syntmp/comp.plg
comp/synthesis/traplog.tlg
comp/viewdraw/vf/project.lst
comp/viewdraw/viewdraw.ini
comp/designer/impl1/comp.dtf
comp/designer/impl1/simulation
comp/designer/impl1
comp/synthesis/backup
comp/synthesis/coreip
comp/synthesis/syntmp
comp/viewdraw/sch
comp/viewdraw/sym
comp/viewdraw/vf
comp/viewdraw/wir
comp/component
comp/constraint
comp/coreconsole
comp/designer
comp/hdl
comp/phy_synthesis
comp/simulation
comp/smartgen
comp/stimulus
comp/synthesis
comp/viewdraw
comp
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