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文件名称:3.VGA

  • 所属分类：
    VHDL-FPGA-Verilog
  • 标签属性：
    [VHDL] [源码]
  • 上传时间：
    2012-11-16
  • 文件大小：
    738.25kb
  • 已下载：
    1次
  • 提 供 者：
    liwe****
  • 相关连接：
    无
  • 下载说明：
    别用迅雷下载，失败请重下，重下不扣分！
修正介绍说明

介绍说明－－下载内容来自于网络，使用问题请自行百度

FPGA驱动VGA接口显示彩虹条的实验，代码VHDL跟Verilog HDL的都有-FPGA drive VGA interface to display
(系统自动生成,下载前可以参看下载内容)

下载文件列表

3.VGA/Verilog/db/prev_cmp_VGA.asm.qmsg
3.VGA/Verilog/db/prev_cmp_VGA.fit.qmsg
3.VGA/Verilog/db/prev_cmp_VGA.map.qmsg
3.VGA/Verilog/db/prev_cmp_VGA.qmsg
3.VGA/Verilog/db/prev_cmp_VGA.tan.qmsg
3.VGA/Verilog/db/VGA.(0).cnf.cdb
3.VGA/Verilog/db/VGA.(0).cnf.hdb
3.VGA/Verilog/db/VGA.asm.qmsg
3.VGA/Verilog/db/VGA.asm_labs.ddb
3.VGA/Verilog/db/VGA.cbx.xml
3.VGA/Verilog/db/VGA.cmp.bpm
3.VGA/Verilog/db/VGA.cmp.cdb
3.VGA/Verilog/db/VGA.cmp.ecobp
3.VGA/Verilog/db/VGA.cmp.hdb
3.VGA/Verilog/db/VGA.cmp.kpt
3.VGA/Verilog/db/VGA.cmp.logdb
3.VGA/Verilog/db/VGA.cmp.rdb
3.VGA/Verilog/db/VGA.cmp.tdb
3.VGA/Verilog/db/VGA.cmp0.ddb
3.VGA/Verilog/db/VGA.cmp2.ddb
3.VGA/Verilog/db/VGA.cmp_merge.kpt
3.VGA/Verilog/db/VGA.db_info
3.VGA/Verilog/db/VGA.eco.cdb
3.VGA/Verilog/db/VGA.fit.qmsg
3.VGA/Verilog/db/VGA.hier_info
3.VGA/Verilog/db/VGA.hif
3.VGA/Verilog/db/VGA.lpc.html
3.VGA/Verilog/db/VGA.lpc.rdb
3.VGA/Verilog/db/VGA.lpc.txt
3.VGA/Verilog/db/VGA.map.bpm
3.VGA/Verilog/db/VGA.map.cdb
3.VGA/Verilog/db/VGA.map.ecobp
3.VGA/Verilog/db/VGA.map.hdb
3.VGA/Verilog/db/VGA.map.kpt
3.VGA/Verilog/db/VGA.map.logdb
3.VGA/Verilog/db/VGA.map.qmsg
3.VGA/Verilog/db/VGA.map_bb.cdb
3.VGA/Verilog/db/VGA.map_bb.hdb
3.VGA/Verilog/db/VGA.map_bb.logdb
3.VGA/Verilog/db/VGA.pre_map.cdb
3.VGA/Verilog/db/VGA.pre_map.hdb
3.VGA/Verilog/db/VGA.rtlv.hdb
3.VGA/Verilog/db/VGA.rtlv_sg.cdb
3.VGA/Verilog/db/VGA.rtlv_sg_swap.cdb
3.VGA/Verilog/db/VGA.sgdiff.cdb
3.VGA/Verilog/db/VGA.sgdiff.hdb
3.VGA/Verilog/db/VGA.sld_design_entry.sci
3.VGA/Verilog/db/VGA.sld_design_entry_dsc.sci
3.VGA/Verilog/db/VGA.syn_hier_info
3.VGA/Verilog/db/VGA.tan.qmsg
3.VGA/Verilog/db/VGA.tis_db_list.ddb
3.VGA/Verilog/db/VGA_global_asgn_op.abo
3.VGA/Verilog/incremental_db/compiled_partitions/VGA.root_partition.cmp.atm
3.VGA/Verilog/incremental_db/compiled_partitions/VGA.root_partition.cmp.dfp
3.VGA/Verilog/incremental_db/compiled_partitions/VGA.root_partition.cmp.hdbx
3.VGA/Verilog/incremental_db/compiled_partitions/VGA.root_partition.cmp.kpt
3.VGA/Verilog/incremental_db/compiled_partitions/VGA.root_partition.cmp.logdb
3.VGA/Verilog/incremental_db/compiled_partitions/VGA.root_partition.cmp.rcf
3.VGA/Verilog/incremental_db/compiled_partitions/VGA.root_partition.map.atm
3.VGA/Verilog/incremental_db/compiled_partitions/VGA.root_partition.map.dpi
3.VGA/Verilog/incremental_db/compiled_partitions/VGA.root_partition.map.hdbx
3.VGA/Verilog/incremental_db/compiled_partitions/VGA.root_partition.map.kpt
3.VGA/Verilog/incremental_db/README
3.VGA/Verilog/pin/CORE2-5SD-PERI1-SLOT1-PERI2-SLOT2.tcl
3.VGA/Verilog/pin/CORE2-5U-PERI1-SLOT1-PERI2-SLOT2.tcl
3.VGA/Verilog/pin/COREC-240U-PERI1-SLOT1-PERI2-SLOT2.tcl
3.VGA/Verilog/VGA.asm.rpt
3.VGA/Verilog/VGA.done
3.VGA/Verilog/VGA.dpf
3.VGA/Verilog/VGA.fit.rpt
3.VGA/Verilog/VGA.fit.smsg
3.VGA/Verilog/VGA.fit.summary
3.VGA/Verilog/VGA.flow.rpt
3.VGA/Verilog/VGA.map.rpt
3.VGA/Verilog/VGA.map.summary
3.VGA/Verilog/VGA.pin
3.VGA/Verilog/VGA.pof
3.VGA/Verilog/VGA.qpf
3.VGA/Verilog/VGA.qsf
3.VGA/Verilog/VGA.qws
3.VGA/Verilog/VGA.sof
3.VGA/Verilog/VGA.tan.rpt
3.VGA/Verilog/VGA.tan.summary
3.VGA/Verilog/VGA.v
3.VGA/Verilog/VGA.v.bak
3.VGA/Verilog/VGA_assignment_defaults.qdf
3.VGA/VHDL/db/prev_cmp_VGA.asm.qmsg
3.VGA/VHDL/db/prev_cmp_VGA.fit.qmsg
3.VGA/VHDL/db/prev_cmp_VGA.map.qmsg
3.VGA/VHDL/db/prev_cmp_VGA.qmsg
3.VGA/VHDL/db/prev_cmp_VGA.tan.qmsg
3.VGA/VHDL/db/VGA.(0).cnf.cdb
3.VGA/VHDL/db/VGA.(0).cnf.hdb
3.VGA/VHDL/db/VGA.asm.qmsg
3.VGA/VHDL/db/VGA.asm_labs.ddb
3.VGA/VHDL/db/VGA.cbx.xml
3.VGA/VHDL/db/VGA.cmp.bpm
3.VGA/VHDL/db/VGA.cmp.cdb
3.VGA/VHDL/db/VGA.cmp.ecobp
3.VGA/VHDL/db/VGA.cmp.hdb
3.VGA/VHDL/db/VGA.cmp.kpt
3.VGA/VHDL/db/VGA.cmp.logdb
3.VGA/VHDL/db/VGA.cmp.rdb
3.VGA/VHDL/db/VGA.cmp.tdb
3.VGA/VHDL/db/VGA.cmp0.ddb
3.VGA/VHDL/db/VGA.cmp2.ddb
3.VGA/VHDL/db/VGA.cmp_merge.kpt
3.VGA/VHDL/db/VGA.db_info
3.VGA/VHDL/db/VGA.eco.cdb
3.VGA/VHDL/db/VGA.fit.qmsg
3.VGA/VHDL/db/VGA.hier_info
3.VGA/VHDL/db/VGA.hif
3.VGA/VHDL/db/VGA.lpc.html
3.VGA/VHDL/db/VGA.lpc.rdb
3.VGA/VHDL/db/VGA.lpc.txt
3.VGA/VHDL/db/VGA.map.bpm
3.VGA/VHDL/db/VGA.map.cdb
3.VGA/VHDL/db/VGA.map.ecobp
3.VGA/VHDL/db/VGA.map.hdb
3.VGA/VHDL/db/VGA.map.kpt
3.VGA/VHDL/db/VGA.map.logdb
3.VGA/VHDL/db/VGA.map.qmsg
3.VGA/VHDL/db/VGA.map_bb.cdb
3.VGA/VHDL/db/VGA.map_bb.hdb
3.VGA/VHDL/db/VGA.map_bb.logdb
3.VGA/VHDL/db/VGA.pre_map.cdb
3.VGA/VHDL/db/VGA.pre_map.hdb
3.VGA/VHDL/db/VGA.rtlv.hdb
3.VGA/VHDL/db/VGA.rtlv_sg.cdb
3.VGA/VHDL/db/VGA.rtlv_sg_swap.cdb
3.VGA/VHDL/db/VGA.sgdiff.cdb
3.VGA/VHDL/db/VGA.sgdiff.hdb
3.VGA/VHDL/db/VGA.sld_design_entry.sci
3.VGA/VHDL/db/VGA.sld_design_entry_dsc.sci
3.VGA/VHDL/db/VGA.syn_hier_info
3.VGA/VHDL/db/VGA.tan.qmsg
3.VGA/VHDL/db/VGA.tis_db_list.ddb
3.VGA/VHDL/db/VGA.tmw_info
3.VGA/VHDL/db/VGA_global_asgn_op.abo
3.VGA/VHDL/incremental_db/compiled_partitions/VGA.root_partition.cmp.atm
3.VGA/VHDL/incremental_db/compiled_partitions/VGA.root_partition.cmp.dfp
3.VGA/VHDL/incremental_db/compiled_partitions/VGA.root_partition.cmp.hdbx
3.VGA/VHDL/incremental_db/compiled_partitions/VGA.root_partition.cmp.kpt
3.VGA/VHDL/incremental_db/compiled_partitions/VGA.root_partition.cmp.logdb
3.VGA/VHDL/incremental_db/compiled_partiti

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