文件名称:1602_CLOCK
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- 上传时间:2012-11-16
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文件大小:2.23mb
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基于FPGA的1602时钟控制,支持时间调整-FPGA,1602 ,clock
(系统自动生成,下载前可以参看下载内容)
下载文件列表
1602_CLOCK/1602_CLOCK.asm.rpt
1602_CLOCK/1602_CLOCK.cdf
1602_CLOCK/1602_CLOCK.done
1602_CLOCK/1602_CLOCK.dpf
1602_CLOCK/1602_CLOCK.eda.rpt
1602_CLOCK/1602_CLOCK.fit.rpt
1602_CLOCK/1602_CLOCK.fit.smsg
1602_CLOCK/1602_CLOCK.fit.summary
1602_CLOCK/1602_CLOCK.flow.rpt
1602_CLOCK/1602_CLOCK.map.rpt
1602_CLOCK/1602_CLOCK.map.smsg
1602_CLOCK/1602_CLOCK.map.summary
1602_CLOCK/1602_CLOCK.pin
1602_CLOCK/1602_CLOCK.pof
1602_CLOCK/1602_CLOCK.qpf
1602_CLOCK/1602_CLOCK.qsf
1602_CLOCK/1602_CLOCK.sof
1602_CLOCK/1602_CLOCK.tan.rpt
1602_CLOCK/1602_CLOCK.tan.summary
1602_CLOCK/1602_CLOCK.v
1602_CLOCK/1602_CLOCK.v.bak
1602_CLOCK/1602_CLOCK_assignment_defaults.qdf
1602_CLOCK/1602_CLOCK_description.txt
1602_CLOCK/1602_CLOCK_nativelink_simulation.rpt
1602_CLOCK/db/1602_CLOCK.db_info
1602_CLOCK/db/1602_CLOCK.sld_design_entry.sci
1602_CLOCK/db/logic_util_heursitic.dat
1602_CLOCK/db/prev_cmp_1602_CLOCK.qmsg
1602_CLOCK/incremental_db/compiled_partitions/1602_CLOCK.db_info
1602_CLOCK/incremental_db/compiled_partitions/1602_CLOCK.root_partition.cmp.dfp
1602_CLOCK/incremental_db/compiled_partitions/1602_CLOCK.root_partition.cmp.kpt
1602_CLOCK/incremental_db/compiled_partitions/1602_CLOCK.root_partition.cmp.logdb
1602_CLOCK/incremental_db/compiled_partitions/1602_CLOCK.root_partition.map.dpi
1602_CLOCK/incremental_db/compiled_partitions/1602_CLOCK.root_partition.map.kpt
1602_CLOCK/incremental_db/README
1602_CLOCK/simulation/modelsim/1602_CLOCK.sft
1602_CLOCK/simulation/modelsim/1602_CLOCK.vo
1602_CLOCK/simulation/modelsim/1602_CLOCK_modelsim.xrf
1602_CLOCK/simulation/modelsim/1602_CLOCK_run_msim_gate_verilog.do
1602_CLOCK/simulation/modelsim/1602_CLOCK_run_msim_rtl_verilog.do
1602_CLOCK/simulation/modelsim/1602_CLOCK_run_msim_rtl_verilog.do.bak
1602_CLOCK/simulation/modelsim/1602_CLOCK_run_msim_rtl_verilog.do.bak1
1602_CLOCK/simulation/modelsim/1602_CLOCK_run_msim_rtl_verilog.do.bak2
1602_CLOCK/simulation/modelsim/1602_CLOCK_run_msim_rtl_verilog.do.bak3
1602_CLOCK/simulation/modelsim/1602_CLOCK_run_msim_rtl_verilog.do.bak4
1602_CLOCK/simulation/modelsim/1602_CLOCK_run_msim_rtl_verilog.do.bak5
1602_CLOCK/simulation/modelsim/1602_CLOCK_run_msim_rtl_verilog.do.bak6
1602_CLOCK/simulation/modelsim/1602_CLOCK_run_msim_rtl_verilog.do.bak7
1602_CLOCK/simulation/modelsim/1602_CLOCK_v.sdo
1602_CLOCK/simulation/modelsim/1602_CLOCK_v.sdo_typ.csd
1602_CLOCK/simulation/modelsim/CLOCK_1602.vt
1602_CLOCK/simulation/modelsim/CLOCK_1602.vt.bak
1602_CLOCK/simulation/modelsim/gate_work/@c@l@o@c@k_1602/verilog.prw
1602_CLOCK/simulation/modelsim/gate_work/@c@l@o@c@k_1602/verilog.psm
1602_CLOCK/simulation/modelsim/gate_work/@c@l@o@c@k_1602/_primary.dat
1602_CLOCK/simulation/modelsim/gate_work/@c@l@o@c@k_1602/_primary.dbs
1602_CLOCK/simulation/modelsim/gate_work/@c@l@o@c@k_1602/_primary.vhd
1602_CLOCK/simulation/modelsim/gate_work/@c@l@o@c@k_1602_vlg_tst/verilog.prw
1602_CLOCK/simulation/modelsim/gate_work/@c@l@o@c@k_1602_vlg_tst/verilog.psm
1602_CLOCK/simulation/modelsim/gate_work/@c@l@o@c@k_1602_vlg_tst/_primary.dat
1602_CLOCK/simulation/modelsim/gate_work/@c@l@o@c@k_1602_vlg_tst/_primary.dbs
1602_CLOCK/simulation/modelsim/gate_work/@c@l@o@c@k_1602_vlg_tst/_primary.vhd
1602_CLOCK/simulation/modelsim/gate_work/_info
1602_CLOCK/simulation/modelsim/gate_work/_vmake
1602_CLOCK/simulation/modelsim/modelsim.ini
1602_CLOCK/simulation/modelsim/msim_transcript
1602_CLOCK/simulation/modelsim/rtl_work/@c@l@o@c@k_1602/verilog.prw
1602_CLOCK/simulation/modelsim/rtl_work/@c@l@o@c@k_1602/verilog.psm
1602_CLOCK/simulation/modelsim/rtl_work/@c@l@o@c@k_1602/_primary.dat
1602_CLOCK/simulation/modelsim/rtl_work/@c@l@o@c@k_1602/_primary.dbs
1602_CLOCK/simulation/modelsim/rtl_work/@c@l@o@c@k_1602/_primary.vhd
1602_CLOCK/simulation/modelsim/rtl_work/@c@l@o@c@k_1602_vlg_tst/verilog.prw
1602_CLOCK/simulation/modelsim/rtl_work/@c@l@o@c@k_1602_vlg_tst/verilog.psm
1602_CLOCK/simulation/modelsim/rtl_work/@c@l@o@c@k_1602_vlg_tst/_primary.dat
1602_CLOCK/simulation/modelsim/rtl_work/@c@l@o@c@k_1602_vlg_tst/_primary.dbs
1602_CLOCK/simulation/modelsim/rtl_work/@c@l@o@c@k_1602_vlg_tst/_primary.vhd
1602_CLOCK/simulation/modelsim/rtl_work/_info
1602_CLOCK/simulation/modelsim/rtl_work/_vmake
1602_CLOCK/simulation/modelsim/vsim.wlf
1602_CLOCK/simulation/modelsim/wlft2y1na1
1602_CLOCK/simulation/modelsim/wlftbsgza3
1602_CLOCK/simulation/modelsim/wlftf78jvy
1602_CLOCK/simulation/modelsim/wlftrjqik8
1602_CLOCK/simulation/modelsim/wlfty4xb50
1602_CLOCK/simulation/modelsim/wlftyz4c5h
1602_CLOCK/simulation/modelsim/gate_work/@c@l@o@c@k_1602
1602_CLOCK/simulation/modelsim/gate_work/@c@l@o@c@k_1602_vlg_tst
1602_CLOCK/simulation/modelsim/gate_work/_temp
1602_CLOCK/simulation/modelsim/rtl_work/@c@l@o@c@k_1602
1602_CLOCK/simulation/modelsim/rtl_work/@c@l@o@c@k_1602_vlg_tst
1602_CLOCK/simulation/modelsim/rtl_work/_temp
1602_CLOCK/simulation/modelsim/gate_work
1602_CLOCK/simulation/modelsim/rtl_work
1602_CLOCK/incremental_db/compiled_partitions
1602_CLOCK/simulation/modelsim
1602_CLOCK/db
1602_CLOCK/incremental_db
1602_CLOCK/simulation
1602_CLOCK
1602_CLOCK/1602_CLOCK.cdf
1602_CLOCK/1602_CLOCK.done
1602_CLOCK/1602_CLOCK.dpf
1602_CLOCK/1602_CLOCK.eda.rpt
1602_CLOCK/1602_CLOCK.fit.rpt
1602_CLOCK/1602_CLOCK.fit.smsg
1602_CLOCK/1602_CLOCK.fit.summary
1602_CLOCK/1602_CLOCK.flow.rpt
1602_CLOCK/1602_CLOCK.map.rpt
1602_CLOCK/1602_CLOCK.map.smsg
1602_CLOCK/1602_CLOCK.map.summary
1602_CLOCK/1602_CLOCK.pin
1602_CLOCK/1602_CLOCK.pof
1602_CLOCK/1602_CLOCK.qpf
1602_CLOCK/1602_CLOCK.qsf
1602_CLOCK/1602_CLOCK.sof
1602_CLOCK/1602_CLOCK.tan.rpt
1602_CLOCK/1602_CLOCK.tan.summary
1602_CLOCK/1602_CLOCK.v
1602_CLOCK/1602_CLOCK.v.bak
1602_CLOCK/1602_CLOCK_assignment_defaults.qdf
1602_CLOCK/1602_CLOCK_description.txt
1602_CLOCK/1602_CLOCK_nativelink_simulation.rpt
1602_CLOCK/db/1602_CLOCK.db_info
1602_CLOCK/db/1602_CLOCK.sld_design_entry.sci
1602_CLOCK/db/logic_util_heursitic.dat
1602_CLOCK/db/prev_cmp_1602_CLOCK.qmsg
1602_CLOCK/incremental_db/compiled_partitions/1602_CLOCK.db_info
1602_CLOCK/incremental_db/compiled_partitions/1602_CLOCK.root_partition.cmp.dfp
1602_CLOCK/incremental_db/compiled_partitions/1602_CLOCK.root_partition.cmp.kpt
1602_CLOCK/incremental_db/compiled_partitions/1602_CLOCK.root_partition.cmp.logdb
1602_CLOCK/incremental_db/compiled_partitions/1602_CLOCK.root_partition.map.dpi
1602_CLOCK/incremental_db/compiled_partitions/1602_CLOCK.root_partition.map.kpt
1602_CLOCK/incremental_db/README
1602_CLOCK/simulation/modelsim/1602_CLOCK.sft
1602_CLOCK/simulation/modelsim/1602_CLOCK.vo
1602_CLOCK/simulation/modelsim/1602_CLOCK_modelsim.xrf
1602_CLOCK/simulation/modelsim/1602_CLOCK_run_msim_gate_verilog.do
1602_CLOCK/simulation/modelsim/1602_CLOCK_run_msim_rtl_verilog.do
1602_CLOCK/simulation/modelsim/1602_CLOCK_run_msim_rtl_verilog.do.bak
1602_CLOCK/simulation/modelsim/1602_CLOCK_run_msim_rtl_verilog.do.bak1
1602_CLOCK/simulation/modelsim/1602_CLOCK_run_msim_rtl_verilog.do.bak2
1602_CLOCK/simulation/modelsim/1602_CLOCK_run_msim_rtl_verilog.do.bak3
1602_CLOCK/simulation/modelsim/1602_CLOCK_run_msim_rtl_verilog.do.bak4
1602_CLOCK/simulation/modelsim/1602_CLOCK_run_msim_rtl_verilog.do.bak5
1602_CLOCK/simulation/modelsim/1602_CLOCK_run_msim_rtl_verilog.do.bak6
1602_CLOCK/simulation/modelsim/1602_CLOCK_run_msim_rtl_verilog.do.bak7
1602_CLOCK/simulation/modelsim/1602_CLOCK_v.sdo
1602_CLOCK/simulation/modelsim/1602_CLOCK_v.sdo_typ.csd
1602_CLOCK/simulation/modelsim/CLOCK_1602.vt
1602_CLOCK/simulation/modelsim/CLOCK_1602.vt.bak
1602_CLOCK/simulation/modelsim/gate_work/@c@l@o@c@k_1602/verilog.prw
1602_CLOCK/simulation/modelsim/gate_work/@c@l@o@c@k_1602/verilog.psm
1602_CLOCK/simulation/modelsim/gate_work/@c@l@o@c@k_1602/_primary.dat
1602_CLOCK/simulation/modelsim/gate_work/@c@l@o@c@k_1602/_primary.dbs
1602_CLOCK/simulation/modelsim/gate_work/@c@l@o@c@k_1602/_primary.vhd
1602_CLOCK/simulation/modelsim/gate_work/@c@l@o@c@k_1602_vlg_tst/verilog.prw
1602_CLOCK/simulation/modelsim/gate_work/@c@l@o@c@k_1602_vlg_tst/verilog.psm
1602_CLOCK/simulation/modelsim/gate_work/@c@l@o@c@k_1602_vlg_tst/_primary.dat
1602_CLOCK/simulation/modelsim/gate_work/@c@l@o@c@k_1602_vlg_tst/_primary.dbs
1602_CLOCK/simulation/modelsim/gate_work/@c@l@o@c@k_1602_vlg_tst/_primary.vhd
1602_CLOCK/simulation/modelsim/gate_work/_info
1602_CLOCK/simulation/modelsim/gate_work/_vmake
1602_CLOCK/simulation/modelsim/modelsim.ini
1602_CLOCK/simulation/modelsim/msim_transcript
1602_CLOCK/simulation/modelsim/rtl_work/@c@l@o@c@k_1602/verilog.prw
1602_CLOCK/simulation/modelsim/rtl_work/@c@l@o@c@k_1602/verilog.psm
1602_CLOCK/simulation/modelsim/rtl_work/@c@l@o@c@k_1602/_primary.dat
1602_CLOCK/simulation/modelsim/rtl_work/@c@l@o@c@k_1602/_primary.dbs
1602_CLOCK/simulation/modelsim/rtl_work/@c@l@o@c@k_1602/_primary.vhd
1602_CLOCK/simulation/modelsim/rtl_work/@c@l@o@c@k_1602_vlg_tst/verilog.prw
1602_CLOCK/simulation/modelsim/rtl_work/@c@l@o@c@k_1602_vlg_tst/verilog.psm
1602_CLOCK/simulation/modelsim/rtl_work/@c@l@o@c@k_1602_vlg_tst/_primary.dat
1602_CLOCK/simulation/modelsim/rtl_work/@c@l@o@c@k_1602_vlg_tst/_primary.dbs
1602_CLOCK/simulation/modelsim/rtl_work/@c@l@o@c@k_1602_vlg_tst/_primary.vhd
1602_CLOCK/simulation/modelsim/rtl_work/_info
1602_CLOCK/simulation/modelsim/rtl_work/_vmake
1602_CLOCK/simulation/modelsim/vsim.wlf
1602_CLOCK/simulation/modelsim/wlft2y1na1
1602_CLOCK/simulation/modelsim/wlftbsgza3
1602_CLOCK/simulation/modelsim/wlftf78jvy
1602_CLOCK/simulation/modelsim/wlftrjqik8
1602_CLOCK/simulation/modelsim/wlfty4xb50
1602_CLOCK/simulation/modelsim/wlftyz4c5h
1602_CLOCK/simulation/modelsim/gate_work/@c@l@o@c@k_1602
1602_CLOCK/simulation/modelsim/gate_work/@c@l@o@c@k_1602_vlg_tst
1602_CLOCK/simulation/modelsim/gate_work/_temp
1602_CLOCK/simulation/modelsim/rtl_work/@c@l@o@c@k_1602
1602_CLOCK/simulation/modelsim/rtl_work/@c@l@o@c@k_1602_vlg_tst
1602_CLOCK/simulation/modelsim/rtl_work/_temp
1602_CLOCK/simulation/modelsim/gate_work
1602_CLOCK/simulation/modelsim/rtl_work
1602_CLOCK/incremental_db/compiled_partitions
1602_CLOCK/simulation/modelsim
1602_CLOCK/db
1602_CLOCK/incremental_db
1602_CLOCK/simulation
1602_CLOCK
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