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文件名称:SDRAM

  • 所属分类：
    VHDL-FPGA-Verilog
  • 标签属性：
    [C/C++] [源码]
  • 上传时间：
    2012-11-16
  • 文件大小：
    12.26mb
  • 已下载：
    0次
  • 提 供 者：
    陈***
  • 相关连接：
    无
  • 下载说明：
    别用迅雷下载，失败请重下，重下不扣分！
修正介绍说明

介绍说明－－下载内容来自于网络，使用问题请自行百度

在ISE环境下对SDRAM(异步动态存储器)的控制模块设计。-In the ISE environment of SDRAM ( asynchronous DRAM ) control module design.
(系统自动生成,下载前可以参看下载内容)

下载文件列表

SDRAM/
SDRAM/123.cpj
SDRAM/Command.vhd
SDRAM/control_interface.vhd
SDRAM/device_usage_statistics.html
SDRAM/fpga_sdram.bgn
SDRAM/fpga_sdram.bit
SDRAM/FPGA_SDRAM.bld
SDRAM/FPGA_SDRAM.cel
SDRAM/FPGA_SDRAM.cmd_log
SDRAM/fpga_sdram.drc
SDRAM/FPGA_SDRAM.lfp
SDRAM/FPGA_SDRAM.lso
SDRAM/fpga_sdram.msd
SDRAM/fpga_sdram.msk
SDRAM/FPGA_SDRAM.ncd
SDRAM/FPGA_SDRAM.ngc
SDRAM/FPGA_SDRAM.ngd
SDRAM/FPGA_SDRAM.ngr
SDRAM/FPGA_SDRAM.pad
SDRAM/FPGA_SDRAM.par
SDRAM/FPGA_SDRAM.pcf
SDRAM/FPGA_SDRAM.prj
SDRAM/fpga_sdram.rbb
SDRAM/fpga_sdram.rbd
SDRAM/FPGA_SDRAM.stx
SDRAM/FPGA_SDRAM.syr
SDRAM/fpga_sdram.twr
SDRAM/fpga_sdram.twx
SDRAM/FPGA_SDRAM.ucf
SDRAM/FPGA_SDRAM.unroutes
SDRAM/FPGA_SDRAM.ut
SDRAM/FPGA_SDRAM.vhd
SDRAM/FPGA_SDRAM.xpi
SDRAM/FPGA_SDRAM.xst
SDRAM/FPGA_SDRAM_cs.blc
SDRAM/FPGA_SDRAM_cs.ngc
SDRAM/FPGA_SDRAM_guide.ncd
SDRAM/FPGA_SDRAM_last_par.ncd
SDRAM/FPGA_SDRAM_map.map
SDRAM/FPGA_SDRAM_map.mrp
SDRAM/FPGA_SDRAM_map.ncd
SDRAM/FPGA_SDRAM_map.ngm
SDRAM/FPGA_SDRAM_pad.csv
SDRAM/FPGA_SDRAM_pad.txt
SDRAM/FPGA_SDRAM_prev_built.ngd
SDRAM/FPGA_SDRAM_summary.html
SDRAM/FPGA_SDRAM_summary.xml
SDRAM/FPGA_SDRAM_usage.xml
SDRAM/FPGA_SDRAM_vhdl.prj
SDRAM/init.vhd
SDRAM/isim/
SDRAM/isim.cmd
SDRAM/isim.hdlsourcefiles
SDRAM/isim.log
SDRAM/isim.tmp_save/
SDRAM/isim.tmp_save/_1
SDRAM/isimwavedata.xwv
SDRAM/isim/unisim.auxlib/
SDRAM/isim/unisim.auxlib/bufg/
SDRAM/isim/unisim.auxlib/bufg/bufg_v.h
SDRAM/isim/unisim.auxlib/bufg/mingw/
SDRAM/isim/unisim.auxlib/bufg/mingw/bufg_v.obj
SDRAM/isim/unisim.auxlib/dcm_adv/
SDRAM/isim/unisim.auxlib/dcm_adv/dcm_adv_v.h
SDRAM/isim/unisim.auxlib/dcm_adv/mingw/
SDRAM/isim/unisim.auxlib/dcm_adv/mingw/dcm_adv_v.obj
SDRAM/isim/unisim.auxlib/dcm_adv_clock_divide_by_2/
SDRAM/isim/unisim.auxlib/dcm_adv_clock_divide_by_2/dcm_adv_clock_divide_by_2_v.h
SDRAM/isim/unisim.auxlib/dcm_adv_clock_divide_by_2/mingw/
SDRAM/isim/unisim.auxlib/dcm_adv_clock_divide_by_2/mingw/dcm_adv_clock_divide_by_2_v.obj
SDRAM/isim/unisim.auxlib/dcm_adv_clock_lost/
SDRAM/isim/unisim.auxlib/dcm_adv_clock_lost/dcm_adv_clock_lost_v.h
SDRAM/isim/unisim.auxlib/dcm_adv_clock_lost/mingw/
SDRAM/isim/unisim.auxlib/dcm_adv_clock_lost/mingw/dcm_adv_clock_lost_v.obj
SDRAM/isim/unisim.auxlib/dcm_adv_maximum_period_check/
SDRAM/isim/unisim.auxlib/dcm_adv_maximum_period_check/dcm_adv_maximum_period_check_v.h
SDRAM/isim/unisim.auxlib/dcm_adv_maximum_period_check/mingw/
SDRAM/isim/unisim.auxlib/dcm_adv_maximum_period_check/mingw/dcm_adv_maximum_period_check_v.obj
SDRAM/isim/unisim.auxlib/hdllib.ref
SDRAM/isim/unisim.auxlib/ibufg/
SDRAM/isim/unisim.auxlib/ibufg/ibufg_v.h
SDRAM/isim/unisim.auxlib/ibufg/mingw/
SDRAM/isim/unisim.auxlib/ibufg/mingw/ibufg_v.obj
SDRAM/isim/unisim.auxlib/vcomponents/
SDRAM/isim/unisim.auxlib/vcomponents/mingw/
SDRAM/isim/unisim.auxlib/vcomponents/mingw/vcomponents.obj
SDRAM/isim/unisim.auxlib/vcomponents/vcomponents.h
SDRAM/isim/unisim.auxlib/vpkg/
SDRAM/isim/unisim.auxlib/vpkg/mingw/
SDRAM/isim/unisim.auxlib/vpkg/mingw/vpkg.obj
SDRAM/isim/unisim.auxlib/vpkg/vpkg.h
SDRAM/isim/work/
SDRAM/isim/work/command/
SDRAM/isim/work/command/mingw/
SDRAM/isim/work/command/mingw/rtl.obj
SDRAM/isim/work/command/rtl.h
SDRAM/isim/work/control_interface/
SDRAM/isim/work/control_interface/mingw/
SDRAM/isim/work/control_interface/mingw/rtl.obj
SDRAM/isim/work/control_interface/rtl.h
SDRAM/isim/work/fpga_sdram/
SDRAM/isim/work/fpga_sdram/behavioral.h
SDRAM/isim/work/fpga_sdram/mingw/
SDRAM/isim/work/fpga_sdram/mingw/behavioral.obj
SDRAM/isim/work/hdllib.ref
SDRAM/isim/work/hdpdeps.ref
SDRAM/isim/work/init/
SDRAM/isim/work/init/behavioral.h
SDRAM/isim/work/init/mingw/
SDRAM/isim/work/init/mingw/behavioral.obj
SDRAM/isim/work/sclk/
SDRAM/isim/work/sclk2/
SDRAM/isim/work/sclk2/behavioral.h
SDRAM/isim/work/sclk2/mingw/
SDRAM/isim/work/sclk2/mingw/behavioral.obj
SDRAM/isim/work/sclk/behavioral.h
SDRAM/isim/work/sclk/mingw/
SDRAM/isim/work/sclk/mingw/behavioral.obj
SDRAM/isim/work/sdr/
SDRAM/isim/work/sdr/mingw/
SDRAM/isim/work/sdr/mingw/testbench_arch.obj
SDRAM/isim/work/sdr/testbench_arch.h
SDRAM/isim/work/sdr/xsimtestbench_arch.cpp
SDRAM/isim/work/sdr_data_path/
SDRAM/isim/work/sdr_data_path/mingw/
SDRAM/isim/work/sdr_data_path/mingw/rtl.obj
SDRAM/isim/work/sdr_data_path/rtl.h
SDRAM/isim/work/sdr_sdram/
SDRAM/isim/work/sdr_sdram/mingw/
SDRAM/isim/work/sdr_sdram/mingw/rtl.obj
SDRAM/isim/work/sdr_sdram/rtl.h
SDRAM/isim/work/sub00/
SDRAM/isim/work/sub00/vhpl00.vho
SDRAM/isim/work/sub00/vhpl01.vho
SDRAM/isim/work/sub00/vhpl02.vho
SDRAM/isim/work/sub00/vhpl03.vho
SDRAM/isim/work/sub00/vhpl04.vho
SDRAM/isim/work/sub00/vhpl05.vho
SDRAM/isim/work/sub00/vhpl06.vho
SDRAM/isim/work/sub00/vhpl07.vho
SDRAM/isim/work/sub00/vhpl08.vho
SDRAM/isim/work/sub00/vhpl09.vho
SDRAM/isim/work/sub00/vhpl10.vho
SDRAM/isim/work/sub00/vhpl11.vho
SDRAM/isim/work/sub00/vhpl12.vho
SDRAM/isim/work/sub00/vhpl13.vho
SDRAM/isim/work/sub00/vhpl14.vho
SDRAM/isim/work/sub00/vhpl15.vho
SDRAM/isim/work/sub00/vhpl16.vho
SDRAM/isim/work/sub00/vhpl17.vho
SDRAM/isim/work/sub00/vhpl18.vho
SDRAM/isim/work/sub00/vhpl19.vho
SDRAM/isim/work/test/
SDRAM/isim/work/test/mingw/
SDRAM/isim/work/test/mingw/testbench_arch.obj
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