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文件名称:PipelineCPU2

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  • 上传时间:
    2012-11-16
  • 文件大小:
    754.01kb
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    1次
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介绍说明--下载内容来自于网络,使用问题请自行百度

Modulsim下Verilog写的五级流水线32位简易CPU-five level pipeline CPU written in Verilog.
(系统自动生成,下载前可以参看下载内容)

下载文件列表

PipelineCPU2/ALU.v
PipelineCPU2/ALU.v.bak
PipelineCPU2/ALU_tb.v
PipelineCPU2/ALU_tb.v.bak
PipelineCPU2/Decode.v
PipelineCPU2/Decode.v.bak
PipelineCPU2/DecodeSim.v
PipelineCPU2/Decode_tb.v
PipelineCPU2/Decode_tb.v.bak
PipelineCPU2/EX.v
PipelineCPU2/EX.v.bak
PipelineCPU2/ID.v
PipelineCPU2/ID.v.bak
PipelineCPU2/IF.v
PipelineCPU2/IF.v.bak
PipelineCPU2/IF2.v
PipelineCPU2/IF_tb.v
PipelineCPU2/InstructionROM.v
PipelineCPU2/InstructionROM.v.bak
PipelineCPU2/lab28/.lso
PipelineCPU2/lab28/ALU.v
PipelineCPU2/lab28/DataRAM.asy
PipelineCPU2/lab28/DataRAM.ngc
PipelineCPU2/lab28/DataRAM.sym
PipelineCPU2/lab28/DataRAM.v
PipelineCPU2/lab28/DataRAM.veo
PipelineCPU2/lab28/DataRAM.vhd
PipelineCPU2/lab28/DataRAM.vho
PipelineCPU2/lab28/DataRAM.xco
PipelineCPU2/lab28/DataRAM_flist.txt
PipelineCPU2/lab28/DataRAM_readme.txt
PipelineCPU2/lab28/DataRAM_xmdf.tcl
PipelineCPU2/lab28/Decode.v
PipelineCPU2/lab28/DecodeSim.v
PipelineCPU2/lab28/EX.v
PipelineCPU2/lab28/ID.v
PipelineCPU2/lab28/IF.v
PipelineCPU2/lab28/InstructionROM.v
PipelineCPU2/lab28/lab28.ise
PipelineCPU2/lab28/lab28.ise_ISE_Backup
PipelineCPU2/lab28/lab28.ntrc_log
PipelineCPU2/lab28/lab28.restore
PipelineCPU2/lab28/mipspipelinecpu.bgn
PipelineCPU2/lab28/mipspipelinecpu.bit
PipelineCPU2/lab28/MipsPipelineCPU.bld
PipelineCPU2/lab28/MipsPipelineCPU.cmd_log
PipelineCPU2/lab28/mipspipelinecpu.drc
PipelineCPU2/lab28/MipsPipelineCPU.lso
PipelineCPU2/lab28/MipsPipelineCPU.ncd
PipelineCPU2/lab28/MipsPipelineCPU.ngc
PipelineCPU2/lab28/MipsPipelineCPU.ngd
PipelineCPU2/lab28/MipsPipelineCPU.ngr
PipelineCPU2/lab28/MipsPipelineCPU.pad
PipelineCPU2/lab28/MipsPipelineCPU.par
PipelineCPU2/lab28/MipsPipelineCPU.pcf
PipelineCPU2/lab28/MipsPipelineCPU.prj
PipelineCPU2/lab28/MipsPipelineCPU.stx
PipelineCPU2/lab28/MipsPipelineCPU.syr
PipelineCPU2/lab28/mipspipelinecpu.twr
PipelineCPU2/lab28/mipspipelinecpu.twx
PipelineCPU2/lab28/MipsPipelineCPU.unroutes
PipelineCPU2/lab28/MipsPipelineCPU.ut
PipelineCPU2/lab28/MipsPipelineCPU.v
PipelineCPU2/lab28/MipsPipelineCPU.xpi
PipelineCPU2/lab28/MipsPipelineCPU.xst
PipelineCPU2/lab28/MipsPipelineCPU_guide.ncd
PipelineCPU2/lab28/MipsPipelineCPU_map.map
PipelineCPU2/lab28/MipsPipelineCPU_map.mrp
PipelineCPU2/lab28/MipsPipelineCPU_map.ncd
PipelineCPU2/lab28/MipsPipelineCPU_map.ngm
PipelineCPU2/lab28/MipsPipelineCPU_pad.csv
PipelineCPU2/lab28/MipsPipelineCPU_pad.txt
PipelineCPU2/lab28/MipsPipelineCPU_prev_built.ngd
PipelineCPU2/lab28/MipsPipelineCPU_summary.html
PipelineCPU2/lab28/MipsPipelineCPU_summary.xml
PipelineCPU2/lab28/MipsPipelineCPU_usage.xml
PipelineCPU2/lab28/PipelineSIM.v
PipelineCPU2/lab28/reg32bit.v
PipelineCPU2/lab28/Registers.v
PipelineCPU2/lab28/templates/coregen.xml
PipelineCPU2/lab28/xst/dump.xst/MipsPipelineCPU.prj/ntrc.scr
PipelineCPU2/lab28/xst/work/hdllib.ref
PipelineCPU2/lab28/xst/work/vlg1E/_data_r_a_m.bin
PipelineCPU2/lab28/xst/work/vlg20/_registers.bin
PipelineCPU2/lab28/xst/work/vlg2A/_a_l_u.bin
PipelineCPU2/lab28/xst/work/vlg2F/_mips_pipeline_c_p_u.bin
PipelineCPU2/lab28/xst/work/vlg30/_decode.bin
PipelineCPU2/lab28/xst/work/vlg31/_e_x.bin
PipelineCPU2/lab28/xst/work/vlg31/_i_d.bin
PipelineCPU2/lab28/xst/work/vlg33/_i_f.bin
PipelineCPU2/lab28/xst/work/vlg7C/_instruction_r_o_m.bin
PipelineCPU2/lab28/_ngo/netlist.lst
PipelineCPU2/lab28/_xmsgs/bitgen.xmsgs
PipelineCPU2/lab28/_xmsgs/map.xmsgs
PipelineCPU2/lab28/_xmsgs/ngdbuild.xmsgs
PipelineCPU2/lab28/_xmsgs/par.xmsgs
PipelineCPU2/lab28/_xmsgs/trce.xmsgs
PipelineCPU2/lab28/_xmsgs/xst.xmsgs
PipelineCPU2/lab28.cr.mti
PipelineCPU2/lab28.mpf
PipelineCPU2/MipsPipelineCPU.v
PipelineCPU2/MipsPipelineCPU.v.bak
PipelineCPU2/MipsPipelineCPU_summary.html
PipelineCPU2/PipelineCPU.ise
PipelineCPU2/PipelineCPU.ise_ISE_Backup
PipelineCPU2/PipelineCPU.restore
PipelineCPU2/PipelineDemo.coe
PipelineCPU2/PipelineSIM.v
PipelineCPU2/PipelineSIM.v.bak
PipelineCPU2/reg32bit.v
PipelineCPU2/Registers.v
PipelineCPU2/Registers.v.bak
PipelineCPU2/top_tb.v
PipelineCPU2/top_tb.v.bak
PipelineCPU2/transcript
PipelineCPU2/vsim.wlf
PipelineCPU2/work/@a@l@u/verilog.asm
PipelineCPU2/work/@a@l@u/_primary.dat
PipelineCPU2/work/@a@l@u/_primary.vhd
PipelineCPU2/work/@a@l@u_tb_v/verilog.asm
PipelineCPU2/work/@a@l@u_tb_v/_primary.dat
PipelineCPU2/work/@a@l@u_tb_v/_primary.vhd
PipelineCPU2/work/@data@r@a@m/verilog.asm
PipelineCPU2/work/@data@r@a@m/_primary.dat
PipelineCPU2/work/@data@r@a@m/_primary.vhd
PipelineCPU2/work/@decode/verilog.asm
PipelineCPU2/work/@decode/_primary.dat
PipelineCPU2/work/@decode/_primary.vhd
PipelineCPU2/work/@decode@sim_v/verilog.asm
PipelineCPU2/work/@decode@sim_v/_primary.dat
PipelineCPU2/work/@decode@sim_v/_primary.vhd
PipelineCPU2/work/@decode_tb_v/verilog.asm
PipelineCPU2/work/@decode_tb_v/_primary.dat
PipelineCPU2/work/@decode_tb_v/_primary.vhd
PipelineCPU2/work/@e@x/verilog.asm
PipelineCPU2/work/@e@x/_primary.dat
PipelineCPU2/work/@e@x/_primary.vhd
PipelineCPU2/work/@i@d/verilog.asm
PipelineCPU2/work/@i@d/_primary.dat
PipelineCPU2/work/@i@d/_primary.vhd
PipelineCPU2/work/@i@f/verilog.asm
PipelineCPU2/work/@i@f/_primary.dat
PipelineCPU2/work/@i@f/_primary.vhd
PipelineCPU2/work/@i@f2/verilog.asm
PipelineCPU2/work

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