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文件名称:VerilogHDL

  • 所属分类：
    VHDL-FPGA-Verilog
  • 标签属性：
    [WORD]
  • 上传时间：
    2012-11-16
  • 文件大小：
    1.98mb
  • 已下载：
    0次
  • 提 供 者：
    zhu***
  • 相关连接：
    无
  • 下载说明：
    别用迅雷下载，失败请重下，重下不扣分！
修正介绍说明

介绍说明－－下载内容来自于网络，使用问题请自行百度

《设计与验证：VerilogHDL》的配套源代码，有丰富的例子，有利于初学者使用-Design and Verification: Verilog HDL "supporting source code, a wealth of examples, for beginners
(系统自动生成,下载前可以参看下载内容)

下载文件列表

设计与验证VerilogHDL光盘文件/Example-2-1/HelloVlog.v
设计与验证VerilogHDL光盘文件/Example-2-1/HelloVlog.vPreview
设计与验证VerilogHDL光盘文件/Example-3-1/FullAdd.v
设计与验证VerilogHDL光盘文件/Example-3-1/transcript
设计与验证VerilogHDL光盘文件/Example-3-2/FullAdd.v
设计与验证VerilogHDL光盘文件/Example-3-3/CRC10.v
设计与验证VerilogHDL光盘文件/Example-4-1/cnt.prd
设计与验证VerilogHDL光盘文件/Example-4-1/cnt.prj
设计与验证VerilogHDL光盘文件/Example-4-1/rev_1/cnt1.edf
设计与验证VerilogHDL光盘文件/Example-4-1/rev_1/cnt1.fse
设计与验证VerilogHDL光盘文件/Example-4-1/rev_1/cnt1.srm
设计与验证VerilogHDL光盘文件/Example-4-1/rev_1/cnt1.srr
设计与验证VerilogHDL光盘文件/Example-4-1/rev_1/cnt1.srs
设计与验证VerilogHDL光盘文件/Example-4-1/rev_1/cnt1.tlg
设计与验证VerilogHDL光盘文件/Example-4-1/rev_1/cnt2.edf
设计与验证VerilogHDL光盘文件/Example-4-1/rev_1/cnt2.fse
设计与验证VerilogHDL光盘文件/Example-4-1/rev_1/cnt2.srm
设计与验证VerilogHDL光盘文件/Example-4-1/rev_1/cnt2.srr
设计与验证VerilogHDL光盘文件/Example-4-1/rev_1/cnt2.srs
设计与验证VerilogHDL光盘文件/Example-4-1/rev_1/cnt2.tlg
设计与验证VerilogHDL光盘文件/Example-4-1/rev_1/cnt3.edf
设计与验证VerilogHDL光盘文件/Example-4-1/rev_1/cnt3.fse
设计与验证VerilogHDL光盘文件/Example-4-1/rev_1/cnt3.srm
设计与验证VerilogHDL光盘文件/Example-4-1/rev_1/cnt3.srr
设计与验证VerilogHDL光盘文件/Example-4-1/rev_1/cnt3.srs
设计与验证VerilogHDL光盘文件/Example-4-1/rev_1/cnt3.tlg
设计与验证VerilogHDL光盘文件/Example-4-1/rev_1/syntmp/cnt1.plg
设计与验证VerilogHDL光盘文件/Example-4-1/rev_1/syntmp/cnt2.msg
设计与验证VerilogHDL光盘文件/Example-4-1/rev_1/syntmp/cnt2.plg
设计与验证VerilogHDL光盘文件/Example-4-1/rev_1/syntmp/cnt3.msg
设计与验证VerilogHDL光盘文件/Example-4-1/rev_1/syntmp/cnt3.plg
设计与验证VerilogHDL光盘文件/Example-4-1/source/cnt1.v
设计与验证VerilogHDL光盘文件/Example-4-1/source/cnt2.v
设计与验证VerilogHDL光盘文件/Example-4-1/source/cnt3.v
设计与验证VerilogHDL光盘文件/Example-4-1/source/syntmp.msg
设计与验证VerilogHDL光盘文件/Example-4-1/示例说明.doc
设计与验证VerilogHDL光盘文件/Example-4-10/bibus/bibus.prd
设计与验证VerilogHDL光盘文件/Example-4-10/bibus/bibus.prj
设计与验证VerilogHDL光盘文件/Example-4-10/bibus/bibus.v
设计与验证VerilogHDL光盘文件/Example-4-10/bibus/decode.v
设计与验证VerilogHDL光盘文件/Example-4-10/bibus/rev_1/bibus.fse
设计与验证VerilogHDL光盘文件/Example-4-10/bibus/rev_1/bibus.srd
设计与验证VerilogHDL光盘文件/Example-4-10/bibus/rev_1/bibus.srm
设计与验证VerilogHDL光盘文件/Example-4-10/bibus/rev_1/bibus.srr
设计与验证VerilogHDL光盘文件/Example-4-10/bibus/rev_1/bibus.srs
设计与验证VerilogHDL光盘文件/Example-4-10/bibus/rev_1/bibus.sxr
设计与验证VerilogHDL光盘文件/Example-4-10/bibus/rev_1/bibus.tcl
设计与验证VerilogHDL光盘文件/Example-4-10/bibus/rev_1/bibus.tlg
设计与验证VerilogHDL光盘文件/Example-4-10/bibus/rev_1/bibus.vqm
设计与验证VerilogHDL光盘文件/Example-4-10/bibus/rev_1/bibus.xrf
设计与验证VerilogHDL光盘文件/Example-4-10/bibus/rev_1/bibus_cons.tcl
设计与验证VerilogHDL光盘文件/Example-4-10/bibus/rev_1/bibus_rm.tcl
设计与验证VerilogHDL光盘文件/Example-4-10/bibus/rev_1/rpt_bibus.areasrr
设计与验证VerilogHDL光盘文件/Example-4-10/bibus/rev_1/rpt_bibus_areasrr.htm
设计与验证VerilogHDL光盘文件/Example-4-10/bibus/rev_1/syntmp/bibus.msg
设计与验证VerilogHDL光盘文件/Example-4-10/bibus/rev_1/syntmp/bibus.plg
设计与验证VerilogHDL光盘文件/Example-4-10/bibus/rev_1/syntmp/bibus_cons_ui.tcl
设计与验证VerilogHDL光盘文件/Example-4-10/bibus/rev_1/verif/bibus.vif
设计与验证VerilogHDL光盘文件/Example-4-10/bibus/syntmp.msg
设计与验证VerilogHDL光盘文件/Example-4-10/complex_bibus/complex_bibus.prd
设计与验证VerilogHDL光盘文件/Example-4-10/complex_bibus/complex_bibus.prj
设计与验证VerilogHDL光盘文件/Example-4-10/complex_bibus/complex_bibus.v
设计与验证VerilogHDL光盘文件/Example-4-10/complex_bibus/complex_bibus2.v
设计与验证VerilogHDL光盘文件/Example-4-10/complex_bibus/counter.v
设计与验证VerilogHDL光盘文件/Example-4-10/complex_bibus/decode.v
设计与验证VerilogHDL光盘文件/Example-4-10/complex_bibus/rev_1/AutoConstraint_complex_bibus.sdc
设计与验证VerilogHDL光盘文件/Example-4-10/complex_bibus/rev_1/complex_bibus.fse
设计与验证VerilogHDL光盘文件/Example-4-10/complex_bibus/rev_1/complex_bibus.srd
设计与验证VerilogHDL光盘文件/Example-4-10/complex_bibus/rev_1/complex_bibus.srm
设计与验证VerilogHDL光盘文件/Example-4-10/complex_bibus/rev_1/complex_bibus.srr
设计与验证VerilogHDL光盘文件/Example-4-10/complex_bibus/rev_1/complex_bibus.srs
设计与验证VerilogHDL光盘文件/Example-4-10/complex_bibus/rev_1/complex_bibus.sxr
设计与验证VerilogHDL光盘文件/Example-4-10/complex_bibus/rev_1/complex_bibus.tcl
设计与验证VerilogHDL光盘文件/Example-4-10/complex_bibus/rev_1/complex_bibus.tlg
设计与验证VerilogHDL光盘文件/Example-4-10/complex_bibus/rev_1/complex_bibus.vqm
设计与验证VerilogHDL光盘文件/Example-4-10/complex_bibus/rev_1/complex_bibus.xrf
设计与验证VerilogHDL光盘文件/Example-4-10/complex_bibus/rev_1/complex_bibus2.fse
设计与验证VerilogHDL光盘文件/Example-4-10/complex_bibus/rev_1/complex_bibus2.srd
设计与验证VerilogHDL光盘文件/Example-4-10/complex_bibus/rev_1/complex_bibus2.srm
设计与验证VerilogHDL光盘文件/Example-4-10/complex_bibus/rev_1/complex_bibus2.srr
设计与验证VerilogHDL光盘文件/Example-4-10/complex_bibus/rev_1/complex_bibus2.srs
设计与验证VerilogHDL光盘文件/Example-4-10/complex_bibus/rev_1/complex_bibus2.sxr
设计与验证VerilogHDL光盘文件/Example-4-10/complex_bibus/rev_1/complex_bibus2.tcl
设计与验证VerilogHDL光盘文件/Example-4-10/complex_bibus/rev_1/complex_bibus2.tlg
设计与验证VerilogHDL光盘文件/Example-4-10/complex_bibus/rev_1/complex_bibus2.vqm
设计与验证VerilogHDL光盘文件/Example-4-10/complex_bibus/rev_1/complex_bibus2.xrf
设计与验证VerilogHDL光盘文件/Example-4-10/complex_bibus/rev_1/complex_bibus2_cons.tcl
设计与验证VerilogHDL光盘文件/Example-4-10/complex_bibus/rev_1/complex_bibus2_rm.tcl
设计与验证VerilogHDL光盘文件/Example-4-10/complex_bibus/rev_1/complex_bibus_cons.tcl
设计与验证VerilogHDL光盘文件/Exa

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