UART/
UART/Project/
UART/Project/Fusion_UART/
UART/Project/Fusion_UART/component/
UART/Project/Fusion_UART/constraint/
UART/Project/Fusion_UART/constraint/uart_test.pdc
UART/Project/Fusion_UART/coreconsole/
UART/Project/Fusion_UART/designer/
UART/Project/Fusion_UART/designer/impl1/
UART/Project/Fusion_UART/designer/impl1/designer.log
UART/Project/Fusion_UART/designer/impl1/designer_genhdl.log
UART/Project/Fusion_UART/designer/impl1/simulation/
UART/Project/Fusion_UART/designer/impl1/uart_test.adb
UART/Project/Fusion_UART/designer/impl1/uart_test.dtf/
UART/Project/Fusion_UART/designer/impl1/uart_test.dtf/verify.log
UART/Project/Fusion_UART/designer/impl1/uart_test.ide_des
UART/Project/Fusion_UART/designer/impl1/uart_test.pdb
UART/Project/Fusion_UART/designer/impl1/uart_test.pdb.depends
UART/Project/Fusion_UART/designer/impl1/uart_test.stp
UART/Project/Fusion_UART/designer/impl1/uart_test.tcl
UART/Project/Fusion_UART/designer/impl1/uart_test_ba.sdf
UART/Project/Fusion_UART/designer/impl1/uart_test_ba.v
UART/Project/Fusion_UART/hdl/
UART/Project/Fusion_UART/hdl/hdlsynchk.tcl
UART/Project/Fusion_UART/hdl/rec.v
UART/Project/Fusion_UART/hdl/send.v
UART/Project/Fusion_UART/hdl/uart_test.v
UART/Project/Fusion_UART/phy_synthesis/
UART/Project/Fusion_UART/simulation/
UART/Project/Fusion_UART/simulation/meminit.dat
UART/Project/Fusion_UART/simulation/modelsim.ini
UART/Project/Fusion_UART/simulation/modelsim.ini.sav
UART/Project/Fusion_UART/smartgen/
UART/Project/Fusion_UART/smartgen/smartgen.aws
UART/Project/Fusion_UART/stimulus/
UART/Project/Fusion_UART/stimulus/BtimErrors.log
UART/Project/Fusion_UART/stimulus/files_to_build.txt
UART/Project/Fusion_UART/stimulus/hdlsynchk.tcl
UART/Project/Fusion_UART/stimulus/uart_test.dsk
UART/Project/Fusion_UART/stimulus/uart_test.hpj
UART/Project/Fusion_UART/stimulus/uart_test.v
UART/Project/Fusion_UART/stimulus/uart_test_tbench.bk
UART/Project/Fusion_UART/stimulus/uart_test_tbench.btim
UART/Project/Fusion_UART/stimulus/uart_test_tbench.v
UART/Project/Fusion_UART/stimulus/waveperl.log
UART/Project/Fusion_UART/synthesis/
UART/Project/Fusion_UART/synthesis/.recordref
UART/Project/Fusion_UART/synthesis/backup/
UART/Project/Fusion_UART/synthesis/rev_1/
UART/Project/Fusion_UART/synthesis/rev_1/backup/
UART/Project/Fusion_UART/synthesis/rev_1/coreip/
UART/Project/Fusion_UART/synthesis/rev_1/run_options.txt
UART/Project/Fusion_UART/synthesis/rev_1/syntmp/
UART/Project/Fusion_UART/synthesis/run_options.txt
UART/Project/Fusion_UART/synthesis/stdout.log
UART/Project/Fusion_UART/synthesis/synthesis_identify/
UART/Project/Fusion_UART/synthesis/synthesis_identify/syntmp/
UART/Project/Fusion_UART/synthesis/synthesis_identify/syntmp/identify.msg
UART/Project/Fusion_UART/synthesis/synthesis_identify/syntmp/uart_test.msg
UART/Project/Fusion_UART/synthesis/synthesis_identify/syntmp/uart_test_flink.htm
UART/Project/Fusion_UART/synthesis/synthesis_identify/uart_test.srs
UART/Project/Fusion_UART/synthesis/synthesis_identify/uart_test.tlg
UART/Project/Fusion_UART/synthesis/syntmp/
UART/Project/Fusion_UART/synthesis/syntmp/sap.log
UART/Project/Fusion_UART/synthesis/syntmp/uart_test.msg
UART/Project/Fusion_UART/synthesis/syntmp/uart_test.plg
UART/Project/Fusion_UART/synthesis/syntmp/uart_test_flink.htm
UART/Project/Fusion_UART/synthesis/syntmp/uart_test_srr.htm
UART/Project/Fusion_UART/synthesis/syntmp/uart_test_toc.htm
UART/Project/Fusion_UART/synthesis/traplog.tlg
UART/Project/Fusion_UART/synthesis/uart_test.areasrr
UART/Project/Fusion_UART/synthesis/uart_test.edn
UART/Project/Fusion_UART/synthesis/uart_test.fse
UART/Project/Fusion_UART/synthesis/uart_test.htm
UART/Project/Fusion_UART/synthesis/uart_test.map
UART/Project/Fusion_UART/synthesis/uart_test.sap
UART/Project/Fusion_UART/synthesis/uart_test.sdf
UART/Project/Fusion_UART/synthesis/uart_test.srd
UART/Project/Fusion_UART/synthesis/uart_test.srm
UART/Project/Fusion_UART/synthesis/uart_test.srr
UART/Project/Fusion_UART/synthesis/uart_test.srs
UART/Project/Fusion_UART/synthesis/uart_test.tlg
UART/Project/Fusion_UART/synthesis/uart_test_drc.rpt
UART/Project/Fusion_UART/synthesis/uart_test_sdc.sdc
UART/Project/Fusion_UART/synthesis/uart_test_syn.prj
UART/Project/Fusion_UART/uart.prj
UART/Project/Fusion_UART/viewdraw/
UART/Project/Fusion_UART/viewdraw/sch/
UART/Project/Fusion_UART/viewdraw/sym/
UART/Project/Fusion_UART/viewdraw/vf/
UART/Project/Fusion_UART/viewdraw/vf/project.lst
UART/Project/Fusion_UART/viewdraw/viewdraw.ini
UART/Project/Fusion_UART/viewdraw/wir/
UART/Source/
UART/Source/Fusion_UART/
UART/Source/Fusion_UART/rec.v
UART/Source/Fusion_UART/send.v
UART/Source/Fusion_UART/uart_test.v