文件名称:fifo
-
所属分类:
- 标签属性:
- 上传时间:2012-11-16
-
文件大小:27.72kb
-
已下载:0次
-
提 供 者:
-
相关连接:无下载说明:别用迅雷下载,失败请重下,重下不扣分!
介绍说明--下载内容来自于网络,使用问题请自行百度
actel 的同步硬件fifo的testbench,初学者可以看一下testbench怎么写的。-the testbench code of actel fpga,it is right for new learner~
(系统自动生成,下载前可以参看下载内容)
下载文件列表
fifo/designer/impl1/newCore.ide_des
fifo/designer/impl1/QWEQW.ide_des
fifo/designer/impl1/top.ide_des
fifo/fifo.prj
fifo/simulation/modelsim.ini
fifo/simulation/modelsim.log
fifo/simulation/presynth/new@core/verilog.prw
fifo/simulation/presynth/new@core/verilog.psm
fifo/simulation/presynth/new@core/_primary.dat
fifo/simulation/presynth/new@core/_primary.dbs
fifo/simulation/presynth/new@core/_primary.vhd
fifo/simulation/presynth/testbench/verilog.prw
fifo/simulation/presynth/testbench/verilog.psm
fifo/simulation/presynth/testbench/_primary.dat
fifo/simulation/presynth/testbench/_primary.dbs
fifo/simulation/presynth/testbench/_primary.vhd
fifo/simulation/presynth/_info
fifo/simulation/presynth/_vmake
fifo/simulation/run.do
fifo/simulation/vsim.wlf
fifo/smartgen/newCore/newCore.cxf
fifo/smartgen/newCore/newCore.gen
fifo/smartgen/newCore/newCore.log
fifo/smartgen/newCore/newCore.v
fifo/smartgen/newCore_work.ixf
fifo/smartgen/smartgen.aws
fifo/stimulus/testbench.v
fifo/viewdraw/vf/project.lst
fifo/viewdraw/viewdraw.ini
fifo/designer/impl1/simulation
fifo/simulation/presynth/new@core
fifo/simulation/presynth/testbench
fifo/simulation/presynth/_temp
fifo/designer/impl1
fifo/simulation/presynth
fifo/smartgen/newCore
fifo/viewdraw/sch
fifo/viewdraw/sym
fifo/viewdraw/vf
fifo/viewdraw/wir
fifo/component
fifo/constraint
fifo/coreconsole
fifo/designer
fifo/hdl
fifo/phy_synthesis
fifo/simulation
fifo/smartgen
fifo/stimulus
fifo/synthesis
fifo/viewdraw
fifo
fifo/designer/impl1/QWEQW.ide_des
fifo/designer/impl1/top.ide_des
fifo/fifo.prj
fifo/simulation/modelsim.ini
fifo/simulation/modelsim.log
fifo/simulation/presynth/new@core/verilog.prw
fifo/simulation/presynth/new@core/verilog.psm
fifo/simulation/presynth/new@core/_primary.dat
fifo/simulation/presynth/new@core/_primary.dbs
fifo/simulation/presynth/new@core/_primary.vhd
fifo/simulation/presynth/testbench/verilog.prw
fifo/simulation/presynth/testbench/verilog.psm
fifo/simulation/presynth/testbench/_primary.dat
fifo/simulation/presynth/testbench/_primary.dbs
fifo/simulation/presynth/testbench/_primary.vhd
fifo/simulation/presynth/_info
fifo/simulation/presynth/_vmake
fifo/simulation/run.do
fifo/simulation/vsim.wlf
fifo/smartgen/newCore/newCore.cxf
fifo/smartgen/newCore/newCore.gen
fifo/smartgen/newCore/newCore.log
fifo/smartgen/newCore/newCore.v
fifo/smartgen/newCore_work.ixf
fifo/smartgen/smartgen.aws
fifo/stimulus/testbench.v
fifo/viewdraw/vf/project.lst
fifo/viewdraw/viewdraw.ini
fifo/designer/impl1/simulation
fifo/simulation/presynth/new@core
fifo/simulation/presynth/testbench
fifo/simulation/presynth/_temp
fifo/designer/impl1
fifo/simulation/presynth
fifo/smartgen/newCore
fifo/viewdraw/sch
fifo/viewdraw/sym
fifo/viewdraw/vf
fifo/viewdraw/wir
fifo/component
fifo/constraint
fifo/coreconsole
fifo/designer
fifo/hdl
fifo/phy_synthesis
fifo/simulation
fifo/smartgen
fifo/stimulus
fifo/synthesis
fifo/viewdraw
fifo
本网站为编程资源及源代码搜集、介绍的搜索网站,版权归原作者所有! 粤ICP备11031372号
1999-2046 搜珍网 All Rights Reserved.