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文件名称:FIFO

  • 所属分类：
    VHDL-FPGA-Verilog
  • 标签属性：
    [VHDL] [源码]
  • 上传时间：
    2012-11-16
  • 文件大小：
    550.07kb
  • 已下载：
    0次
  • 提 供 者：
    xie****
  • 相关连接：
    无
  • 下载说明：
    别用迅雷下载，失败请重下，重下不扣分！
修正介绍说明

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这是本人学习FPGA时亲自原创的代码，实现的是8x8的fifo结构，采用同步的FIFO结构，仿真测试已经成功！-This is I learn when the original code FPGA in person, the realization of 8 x8 is the fifo structure, the synchronization of the fifo structure, the simulation test is a success!
(系统自动生成,下载前可以参看下载内容)

下载文件列表

FIFO/db/FIFO_8X8.(0).cnf.cdb
FIFO/db/FIFO_8X8.(0).cnf.hdb
FIFO/db/FIFO_8X8.asm.qmsg
FIFO/db/FIFO_8X8.asm.rdb
FIFO/db/FIFO_8X8.asm_labs.ddb
FIFO/db/FIFO_8X8.cbx.xml
FIFO/db/FIFO_8X8.cmp.bpm
FIFO/db/FIFO_8X8.cmp.cdb
FIFO/db/FIFO_8X8.cmp.ecobp
FIFO/db/FIFO_8X8.cmp.hdb
FIFO/db/FIFO_8X8.cmp.kpt
FIFO/db/FIFO_8X8.cmp.logdb
FIFO/db/FIFO_8X8.cmp.rdb
FIFO/db/FIFO_8X8.cmp.tdb
FIFO/db/FIFO_8X8.cmp0.ddb
FIFO/db/FIFO_8X8.cmp2.ddb
FIFO/db/FIFO_8X8.cmp_merge.kpt
FIFO/db/FIFO_8X8.db_info
FIFO/db/FIFO_8X8.eco.cdb
FIFO/db/FIFO_8X8.eda.qmsg
FIFO/db/FIFO_8X8.fit.qmsg
FIFO/db/FIFO_8X8.hier_info
FIFO/db/FIFO_8X8.hif
FIFO/db/FIFO_8X8.lpc.html
FIFO/db/FIFO_8X8.lpc.rdb
FIFO/db/FIFO_8X8.lpc.txt
FIFO/db/FIFO_8X8.map.bpm
FIFO/db/FIFO_8X8.map.cdb
FIFO/db/FIFO_8X8.map.ecobp
FIFO/db/FIFO_8X8.map.hdb
FIFO/db/FIFO_8X8.map.kpt
FIFO/db/FIFO_8X8.map.logdb
FIFO/db/FIFO_8X8.map.qmsg
FIFO/db/FIFO_8X8.map_bb.cdb
FIFO/db/FIFO_8X8.map_bb.hdb
FIFO/db/FIFO_8X8.map_bb.logdb
FIFO/db/FIFO_8X8.pre_map.cdb
FIFO/db/FIFO_8X8.pre_map.hdb
FIFO/db/FIFO_8X8.rpp.qmsg
FIFO/db/FIFO_8X8.rtlv.hdb
FIFO/db/FIFO_8X8.rtlv_sg.cdb
FIFO/db/FIFO_8X8.rtlv_sg_swap.cdb
FIFO/db/FIFO_8X8.sgate.rvd
FIFO/db/FIFO_8X8.sgate_sm.rvd
FIFO/db/FIFO_8X8.sgdiff.cdb
FIFO/db/FIFO_8X8.sgdiff.hdb
FIFO/db/FIFO_8X8.sld_design_entry.sci
FIFO/db/FIFO_8X8.sld_design_entry_dsc.sci
FIFO/db/FIFO_8X8.smart_action.txt
FIFO/db/FIFO_8X8.syn_hier_info
FIFO/db/FIFO_8X8.tan.qmsg
FIFO/db/FIFO_8X8.tis_db_list.ddb
FIFO/db/FIFO_8X8.tmw_info
FIFO/db/logic_util_heursitic.dat
FIFO/db/prev_cmp_FIFO_8X8.asm.qmsg
FIFO/db/prev_cmp_FIFO_8X8.eda.qmsg
FIFO/db/prev_cmp_FIFO_8X8.fit.qmsg
FIFO/db/prev_cmp_FIFO_8X8.map.qmsg
FIFO/db/prev_cmp_FIFO_8X8.qmsg
FIFO/db/prev_cmp_FIFO_8X8.tan.qmsg
FIFO/FIFO_8X8.asm.rpt
FIFO/FIFO_8X8.done
FIFO/FIFO_8X8.eda.rpt
FIFO/FIFO_8X8.fit.rpt
FIFO/FIFO_8X8.fit.summary
FIFO/FIFO_8X8.flow.rpt
FIFO/FIFO_8X8.map.rpt
FIFO/FIFO_8X8.map.smsg
FIFO/FIFO_8X8.map.summary
FIFO/FIFO_8X8.pin
FIFO/FIFO_8X8.pof
FIFO/FIFO_8X8.qpf
FIFO/FIFO_8X8.qsf
FIFO/FIFO_8X8.qws
FIFO/FIFO_8X8.sof
FIFO/FIFO_8X8.tan.rpt
FIFO/FIFO_8X8.tan.summary
FIFO/FIFO_8X8.V
FIFO/FIFO_8X8.V.bak
FIFO/FIFO_8X8_nativelink_simulation.rpt
FIFO/incremental_db/compiled_partitions/FIFO_8X8.root_partition.cmp.cdb
FIFO/incremental_db/compiled_partitions/FIFO_8X8.root_partition.cmp.dfp
FIFO/incremental_db/compiled_partitions/FIFO_8X8.root_partition.cmp.hdb
FIFO/incremental_db/compiled_partitions/FIFO_8X8.root_partition.cmp.kpt
FIFO/incremental_db/compiled_partitions/FIFO_8X8.root_partition.cmp.logdb
FIFO/incremental_db/compiled_partitions/FIFO_8X8.root_partition.cmp.rcfdb
FIFO/incremental_db/compiled_partitions/FIFO_8X8.root_partition.cmp.re.rcfdb
FIFO/incremental_db/compiled_partitions/FIFO_8X8.root_partition.map.cdb
FIFO/incremental_db/compiled_partitions/FIFO_8X8.root_partition.map.dpi
FIFO/incremental_db/compiled_partitions/FIFO_8X8.root_partition.map.hdb
FIFO/incremental_db/compiled_partitions/FIFO_8X8.root_partition.map.kpt
FIFO/incremental_db/README
FIFO/simulation/modelsim/FIFO_8X8.sft
FIFO/simulation/modelsim/FIFO_8X8.vo
FIFO/simulation/modelsim/FIFO_8X8.vt
FIFO/simulation/modelsim/FIFO_8X8.vt.bak
FIFO/simulation/modelsim/FIFO_8X8_modelsim.xrf
FIFO/simulation/modelsim/FIFO_8X8_run_msim_rtl_verilog.do
FIFO/simulation/modelsim/FIFO_8X8_run_msim_rtl_verilog.do.bak
FIFO/simulation/modelsim/FIFO_8X8_run_msim_rtl_verilog.do.bak1
FIFO/simulation/modelsim/FIFO_8X8_run_msim_rtl_verilog.do.bak10
FIFO/simulation/modelsim/FIFO_8X8_run_msim_rtl_verilog.do.bak2
FIFO/simulation/modelsim/FIFO_8X8_run_msim_rtl_verilog.do.bak3
FIFO/simulation/modelsim/FIFO_8X8_run_msim_rtl_verilog.do.bak4
FIFO/simulation/modelsim/FIFO_8X8_run_msim_rtl_verilog.do.bak5
FIFO/simulation/modelsim/FIFO_8X8_run_msim_rtl_verilog.do.bak6
FIFO/simulation/modelsim/FIFO_8X8_run_msim_rtl_verilog.do.bak7
FIFO/simulation/modelsim/FIFO_8X8_run_msim_rtl_verilog.do.bak8
FIFO/simulation/modelsim/FIFO_8X8_run_msim_rtl_verilog.do.bak9
FIFO/simulation/modelsim/FIFO_8X8_v.sdo
FIFO/simulation/modelsim/modelsim.ini
FIFO/simulation/modelsim/msim_transcript
FIFO/simulation/modelsim/rtl_work/@f@i@f@o_8@x8/verilog.prw
FIFO/simulation/modelsim/rtl_work/@f@i@f@o_8@x8/verilog.psm
FIFO/simulation/modelsim/rtl_work/@f@i@f@o_8@x8/_primary.dat
FIFO/simulation/modelsim/rtl_work/@f@i@f@o_8@x8/_primary.dbs
FIFO/simulation/modelsim/rtl_work/@f@i@f@o_8@x8/_primary.vhd
FIFO/simulation/modelsim/rtl_work/@f@i@f@o_8@x8_vlg_tst/verilog.prw
FIFO/simulation/modelsim/rtl_work/@f@i@f@o_8@x8_vlg_tst/verilog.psm
FIFO/simulation/modelsim/rtl_work/@f@i@f@o_8@x8_vlg_tst/_primary.dat
FIFO/simulation/modelsim/rtl_work/@f@i@f@o_8@x8_vlg_tst/_primary.dbs
FIFO/simulation/modelsim/rtl_work/@f@i@f@o_8@x8_vlg_tst/_primary.vhd
FIFO/simulation/modelsim/rtl_work/_info
FIFO/simulation/modelsim/rtl_work/_vmake
FIFO/simulation/modelsim/vsim.wlf
FIFO/simulation/modelsim/rtl_work/@f@i@f@o_8@x8
FIFO/simulation/modelsim/rtl_work/@f@i@f@o_8@x8_vlg_tst
FIFO/simulation/modelsim/rtl_work/_temp
FIFO/simulation/modelsim/rtl_work
FIFO/incremental_db/compiled_partitions
FIFO/simulation/modelsim
FIFO/db
FIFO/incremental_db
FIFO/simulation
FIFO

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