文件名称:DDR-SDRAM
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- 上传时间:2012-11-16
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文件大小:876.2kb
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DDR SDRAM的设计,包括DDR SDRAM控制器,以及Modelsim仿真-The design of DDR SDRAM, DDR SDRAM controller, and Modelsim simulation
(系统自动生成,下载前可以参看下载内容)
下载文件列表
DDR SDRAM/doc/ddr_sdram.pdf
DDR SDRAM/model/mt46v4m16.vhd
DDR SDRAM/model/mti_pkg.vhd
DDR SDRAM/readme.txt
DDR SDRAM/route/ddr_sdram.csf
DDR SDRAM/route/ddr_sdram.esf
DDR SDRAM/route/ddr_sdram.psf
DDR SDRAM/route/ddr_sdram.quartus
DDR SDRAM/route/ddr_sdram.vqm
DDR SDRAM/route/pll1.vhd
DDR SDRAM/simulation/APEX20KE_MF.VHD
DDR SDRAM/simulation/ddr_command.vhd
DDR SDRAM/simulation/ddr_control_interface.vhd
DDR SDRAM/simulation/ddr_data_path.vhd
DDR SDRAM/simulation/ddr_sdram.vhd
DDR SDRAM/simulation/ddr_sdram_tb.vhd
DDR SDRAM/simulation/io_utils.vhd
DDR SDRAM/simulation/lpm_pack.vhd
DDR SDRAM/simulation/modelsim.ini
DDR SDRAM/simulation/mt46v4m16.vhd
DDR SDRAM/simulation/mti_pkg.bak
DDR SDRAM/simulation/mti_pkg.vhd
DDR SDRAM/simulation/pll1.vhd
DDR SDRAM/simulation/readme.txt
DDR SDRAM/simulation/stdlogar.vhd
DDR SDRAM/simulation/util1164.vhd
DDR SDRAM/simulation/wave.do
DDR SDRAM/simulation/work/altcam/behave.dat
DDR SDRAM/simulation/work/altcam/behave.psm
DDR SDRAM/simulation/work/altcam/_primary.dat
DDR SDRAM/simulation/work/altclklock/behavior.dat
DDR SDRAM/simulation/work/altclklock/behavior.psm
DDR SDRAM/simulation/work/altclklock/_primary.dat
DDR SDRAM/simulation/work/altlvds_rx/behavior.dat
DDR SDRAM/simulation/work/altlvds_rx/behavior.psm
DDR SDRAM/simulation/work/altlvds_rx/_primary.dat
DDR SDRAM/simulation/work/altlvds_tx/behavior.dat
DDR SDRAM/simulation/work/altlvds_tx/behavior.psm
DDR SDRAM/simulation/work/altlvds_tx/_primary.dat
DDR SDRAM/simulation/work/command/rtl.dat
DDR SDRAM/simulation/work/command/rtl.psm
DDR SDRAM/simulation/work/command/_primary.dat
DDR SDRAM/simulation/work/control_interface/rtl.dat
DDR SDRAM/simulation/work/control_interface/rtl.psm
DDR SDRAM/simulation/work/control_interface/_primary.dat
DDR SDRAM/simulation/work/ddr_command/rtl.dat
DDR SDRAM/simulation/work/ddr_command/rtl.psm
DDR SDRAM/simulation/work/ddr_command/_primary.dat
DDR SDRAM/simulation/work/ddr_control_interface/rtl.dat
DDR SDRAM/simulation/work/ddr_control_interface/rtl.psm
DDR SDRAM/simulation/work/ddr_control_interface/_primary.dat
DDR SDRAM/simulation/work/ddr_data_path/rtl.dat
DDR SDRAM/simulation/work/ddr_data_path/rtl.psm
DDR SDRAM/simulation/work/ddr_data_path/_primary.dat
DDR SDRAM/simulation/work/ddr_sdram/rtl.dat
DDR SDRAM/simulation/work/ddr_sdram/rtl.psm
DDR SDRAM/simulation/work/ddr_sdram/_primary.dat
DDR SDRAM/simulation/work/ddr_sdram_tb/rtl.dat
DDR SDRAM/simulation/work/ddr_sdram_tb/rtl.psm
DDR SDRAM/simulation/work/ddr_sdram_tb/_primary.dat
DDR SDRAM/simulation/work/io_utils/body.dat
DDR SDRAM/simulation/work/io_utils/body.psm
DDR SDRAM/simulation/work/io_utils/_primary.dat
DDR SDRAM/simulation/work/io_utils/_vhdl.psm
DDR SDRAM/simulation/work/lpm_components/body.dat
DDR SDRAM/simulation/work/lpm_components/body.psm
DDR SDRAM/simulation/work/lpm_components/_primary.dat
DDR SDRAM/simulation/work/lpm_components/_vhdl.psm
DDR SDRAM/simulation/work/mt46v4m16/behave.dat
DDR SDRAM/simulation/work/mt46v4m16/behave.psm
DDR SDRAM/simulation/work/mt46v4m16/_primary.dat
DDR SDRAM/simulation/work/mti_pkg/body.dat
DDR SDRAM/simulation/work/mti_pkg/body.psm
DDR SDRAM/simulation/work/mti_pkg/_primary.dat
DDR SDRAM/simulation/work/mti_pkg/_vhdl.psm
DDR SDRAM/simulation/work/pll1/syn.dat
DDR SDRAM/simulation/work/pll1/syn.psm
DDR SDRAM/simulation/work/pll1/_primary.dat
DDR SDRAM/simulation/work/std_logic_arith/body.dat
DDR SDRAM/simulation/work/std_logic_arith/body.psm
DDR SDRAM/simulation/work/std_logic_arith/_primary.dat
DDR SDRAM/simulation/work/std_logic_arith/_vhdl.psm
DDR SDRAM/simulation/work/util_1164/body.dat
DDR SDRAM/simulation/work/util_1164/body.psm
DDR SDRAM/simulation/work/util_1164/_primary.dat
DDR SDRAM/simulation/work/util_1164/_vhdl.psm
DDR SDRAM/simulation/work/_info
DDR SDRAM/source/ddr_command.vhd
DDR SDRAM/source/ddr_control_interface.vhd
DDR SDRAM/source/ddr_data_path.vhd
DDR SDRAM/source/ddr_sdram.vhd
DDR SDRAM/synthesis/synplicity/ddr_sdram.prj
DDR SDRAM/synthesis/synplicity/rev_1/ddr_sdram.srm
DDR SDRAM/synthesis/synplicity/rev_1/ddr_sdram.srr
DDR SDRAM/synthesis/synplicity/rev_1/ddr_sdram.srs
DDR SDRAM/synthesis/synplicity/rev_1/ddr_sdram.tcl
DDR SDRAM/synthesis/synplicity/rev_1/ddr_sdram.tlg
DDR SDRAM/synthesis/synplicity/rev_1/ddr_sdram.vqm
DDR SDRAM/synthesis/synplicity/rev_1/ddr_sdram.xrf
DDR SDRAM/synthesis/synplicity/rev_1/ddr_sdram_cons.tcl
DDR SDRAM/synthesis/synplicity/rev_1/ddr_sdram_rm.tcl
DDR SDRAM/simulation/work/altcam
DDR SDRAM/simulation/work/altclklock
DDR SDRAM/simulation/work/altlvds_rx
DDR SDRAM/simulation/work/altlvds_tx
DDR SDRAM/simulation/work/command
DDR SDRAM/simulation/work/control_interface
DDR SDRAM/simulation/work/ddr_command
DDR SDRAM/simulation/work/ddr_control_interface
DDR SDRAM/simulation/work/ddr_data_path
DDR SDRAM/simulation/work/ddr_sdram
DDR SDRAM/simulation/work/ddr_sdram_tb
DDR SDRAM/simulation/work/io_utils
DDR SDRAM/simulation/work/lpm_components
DDR SDRAM/simulation/work/mt46v4m16
DDR SDRAM/simulation/work/mti_pkg
DDR SDRAM/simulation/work/pll1
DDR SDRAM/simulation/work/std_logic_arith
DDR SDRAM/simulation/work/util_1164
DDR SDRAM/synthesis/synplicit
DDR SDRAM/model/mt46v4m16.vhd
DDR SDRAM/model/mti_pkg.vhd
DDR SDRAM/readme.txt
DDR SDRAM/route/ddr_sdram.csf
DDR SDRAM/route/ddr_sdram.esf
DDR SDRAM/route/ddr_sdram.psf
DDR SDRAM/route/ddr_sdram.quartus
DDR SDRAM/route/ddr_sdram.vqm
DDR SDRAM/route/pll1.vhd
DDR SDRAM/simulation/APEX20KE_MF.VHD
DDR SDRAM/simulation/ddr_command.vhd
DDR SDRAM/simulation/ddr_control_interface.vhd
DDR SDRAM/simulation/ddr_data_path.vhd
DDR SDRAM/simulation/ddr_sdram.vhd
DDR SDRAM/simulation/ddr_sdram_tb.vhd
DDR SDRAM/simulation/io_utils.vhd
DDR SDRAM/simulation/lpm_pack.vhd
DDR SDRAM/simulation/modelsim.ini
DDR SDRAM/simulation/mt46v4m16.vhd
DDR SDRAM/simulation/mti_pkg.bak
DDR SDRAM/simulation/mti_pkg.vhd
DDR SDRAM/simulation/pll1.vhd
DDR SDRAM/simulation/readme.txt
DDR SDRAM/simulation/stdlogar.vhd
DDR SDRAM/simulation/util1164.vhd
DDR SDRAM/simulation/wave.do
DDR SDRAM/simulation/work/altcam/behave.dat
DDR SDRAM/simulation/work/altcam/behave.psm
DDR SDRAM/simulation/work/altcam/_primary.dat
DDR SDRAM/simulation/work/altclklock/behavior.dat
DDR SDRAM/simulation/work/altclklock/behavior.psm
DDR SDRAM/simulation/work/altclklock/_primary.dat
DDR SDRAM/simulation/work/altlvds_rx/behavior.dat
DDR SDRAM/simulation/work/altlvds_rx/behavior.psm
DDR SDRAM/simulation/work/altlvds_rx/_primary.dat
DDR SDRAM/simulation/work/altlvds_tx/behavior.dat
DDR SDRAM/simulation/work/altlvds_tx/behavior.psm
DDR SDRAM/simulation/work/altlvds_tx/_primary.dat
DDR SDRAM/simulation/work/command/rtl.dat
DDR SDRAM/simulation/work/command/rtl.psm
DDR SDRAM/simulation/work/command/_primary.dat
DDR SDRAM/simulation/work/control_interface/rtl.dat
DDR SDRAM/simulation/work/control_interface/rtl.psm
DDR SDRAM/simulation/work/control_interface/_primary.dat
DDR SDRAM/simulation/work/ddr_command/rtl.dat
DDR SDRAM/simulation/work/ddr_command/rtl.psm
DDR SDRAM/simulation/work/ddr_command/_primary.dat
DDR SDRAM/simulation/work/ddr_control_interface/rtl.dat
DDR SDRAM/simulation/work/ddr_control_interface/rtl.psm
DDR SDRAM/simulation/work/ddr_control_interface/_primary.dat
DDR SDRAM/simulation/work/ddr_data_path/rtl.dat
DDR SDRAM/simulation/work/ddr_data_path/rtl.psm
DDR SDRAM/simulation/work/ddr_data_path/_primary.dat
DDR SDRAM/simulation/work/ddr_sdram/rtl.dat
DDR SDRAM/simulation/work/ddr_sdram/rtl.psm
DDR SDRAM/simulation/work/ddr_sdram/_primary.dat
DDR SDRAM/simulation/work/ddr_sdram_tb/rtl.dat
DDR SDRAM/simulation/work/ddr_sdram_tb/rtl.psm
DDR SDRAM/simulation/work/ddr_sdram_tb/_primary.dat
DDR SDRAM/simulation/work/io_utils/body.dat
DDR SDRAM/simulation/work/io_utils/body.psm
DDR SDRAM/simulation/work/io_utils/_primary.dat
DDR SDRAM/simulation/work/io_utils/_vhdl.psm
DDR SDRAM/simulation/work/lpm_components/body.dat
DDR SDRAM/simulation/work/lpm_components/body.psm
DDR SDRAM/simulation/work/lpm_components/_primary.dat
DDR SDRAM/simulation/work/lpm_components/_vhdl.psm
DDR SDRAM/simulation/work/mt46v4m16/behave.dat
DDR SDRAM/simulation/work/mt46v4m16/behave.psm
DDR SDRAM/simulation/work/mt46v4m16/_primary.dat
DDR SDRAM/simulation/work/mti_pkg/body.dat
DDR SDRAM/simulation/work/mti_pkg/body.psm
DDR SDRAM/simulation/work/mti_pkg/_primary.dat
DDR SDRAM/simulation/work/mti_pkg/_vhdl.psm
DDR SDRAM/simulation/work/pll1/syn.dat
DDR SDRAM/simulation/work/pll1/syn.psm
DDR SDRAM/simulation/work/pll1/_primary.dat
DDR SDRAM/simulation/work/std_logic_arith/body.dat
DDR SDRAM/simulation/work/std_logic_arith/body.psm
DDR SDRAM/simulation/work/std_logic_arith/_primary.dat
DDR SDRAM/simulation/work/std_logic_arith/_vhdl.psm
DDR SDRAM/simulation/work/util_1164/body.dat
DDR SDRAM/simulation/work/util_1164/body.psm
DDR SDRAM/simulation/work/util_1164/_primary.dat
DDR SDRAM/simulation/work/util_1164/_vhdl.psm
DDR SDRAM/simulation/work/_info
DDR SDRAM/source/ddr_command.vhd
DDR SDRAM/source/ddr_control_interface.vhd
DDR SDRAM/source/ddr_data_path.vhd
DDR SDRAM/source/ddr_sdram.vhd
DDR SDRAM/synthesis/synplicity/ddr_sdram.prj
DDR SDRAM/synthesis/synplicity/rev_1/ddr_sdram.srm
DDR SDRAM/synthesis/synplicity/rev_1/ddr_sdram.srr
DDR SDRAM/synthesis/synplicity/rev_1/ddr_sdram.srs
DDR SDRAM/synthesis/synplicity/rev_1/ddr_sdram.tcl
DDR SDRAM/synthesis/synplicity/rev_1/ddr_sdram.tlg
DDR SDRAM/synthesis/synplicity/rev_1/ddr_sdram.vqm
DDR SDRAM/synthesis/synplicity/rev_1/ddr_sdram.xrf
DDR SDRAM/synthesis/synplicity/rev_1/ddr_sdram_cons.tcl
DDR SDRAM/synthesis/synplicity/rev_1/ddr_sdram_rm.tcl
DDR SDRAM/simulation/work/altcam
DDR SDRAM/simulation/work/altclklock
DDR SDRAM/simulation/work/altlvds_rx
DDR SDRAM/simulation/work/altlvds_tx
DDR SDRAM/simulation/work/command
DDR SDRAM/simulation/work/control_interface
DDR SDRAM/simulation/work/ddr_command
DDR SDRAM/simulation/work/ddr_control_interface
DDR SDRAM/simulation/work/ddr_data_path
DDR SDRAM/simulation/work/ddr_sdram
DDR SDRAM/simulation/work/ddr_sdram_tb
DDR SDRAM/simulation/work/io_utils
DDR SDRAM/simulation/work/lpm_components
DDR SDRAM/simulation/work/mt46v4m16
DDR SDRAM/simulation/work/mti_pkg
DDR SDRAM/simulation/work/pll1
DDR SDRAM/simulation/work/std_logic_arith
DDR SDRAM/simulation/work/util_1164
DDR SDRAM/synthesis/synplicit
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