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文件名称:Example-b4-1

  • 所属分类：
    VHDL-FPGA-Verilog
  • 标签属性：
    [VHDL] [源码]
  • 上传时间：
    2012-11-16
  • 文件大小：
    6.97mb
  • 已下载：
    1次
  • 提 供 者：
    颜****
  • 相关连接：
    无
  • 下载说明：
    别用迅雷下载，失败请重下，重下不扣分！
修正介绍说明

介绍说明－－下载内容来自于网络，使用问题请自行百度

1.　　定制一个双端口RAM，DualPortRAM

2.　　在顶层工程中实例化这个RAM

3.　　实现这个工程，在Quartus II仿真器中做门级仿真

4.　　在ModelSim中对这个工程进行RTL级仿真

-Customize a dual port RAM, DualPortRAM

On the top floor of the RAM engineering instantiation

To realize the project, in Quartus II simulation implement in to make the door level simulation

In ModelSim project to the RTL simulation
(系统自动生成,下载前可以参看下载内容)

下载文件列表

Example-b4-1/
Example-b4-1/Project/
Example-b4-1/Project/db/
Example-b4-1/Project/db/altsyncram_9gg1.tdf
Example-b4-1/Project/db/logic_util_heursitic.dat
Example-b4-1/Project/db/prev_cmp_TOP.qmsg
Example-b4-1/Project/db/prev_cmp_TOP.sim.qmsg
Example-b4-1/Project/db/TOP.(0).cnf.cdb
Example-b4-1/Project/db/TOP.(0).cnf.hdb
Example-b4-1/Project/db/TOP.(1).cnf.cdb
Example-b4-1/Project/db/TOP.(1).cnf.hdb
Example-b4-1/Project/db/TOP.(2).cnf.cdb
Example-b4-1/Project/db/TOP.(2).cnf.hdb
Example-b4-1/Project/db/TOP.(3).cnf.cdb
Example-b4-1/Project/db/TOP.(3).cnf.hdb
Example-b4-1/Project/db/TOP.asm.qmsg
Example-b4-1/Project/db/TOP.asm.rdb
Example-b4-1/Project/db/TOP.cbx.xml
Example-b4-1/Project/db/TOP.cmp.cdb
Example-b4-1/Project/db/TOP.cmp.hdb
Example-b4-1/Project/db/TOP.cmp.kpt
Example-b4-1/Project/db/TOP.cmp.logdb
Example-b4-1/Project/db/TOP.cmp.rdb
Example-b4-1/Project/db/TOP.cmp.tdb
Example-b4-1/Project/db/TOP.cmp0.ddb
Example-b4-1/Project/db/TOP.db_info
Example-b4-1/Project/db/TOP.eco.cdb
Example-b4-1/Project/db/TOP.eds_overflow
Example-b4-1/Project/db/TOP.fit.qmsg
Example-b4-1/Project/db/TOP.hier_info
Example-b4-1/Project/db/TOP.hif
Example-b4-1/Project/db/TOP.lpc.html
Example-b4-1/Project/db/TOP.lpc.rdb
Example-b4-1/Project/db/TOP.lpc.txt
Example-b4-1/Project/db/TOP.map.cdb
Example-b4-1/Project/db/TOP.map.hdb
Example-b4-1/Project/db/TOP.map.logdb
Example-b4-1/Project/db/TOP.map.qmsg
Example-b4-1/Project/db/TOP.pre_map.cdb
Example-b4-1/Project/db/TOP.pre_map.hdb
Example-b4-1/Project/db/TOP.rtlv.hdb
Example-b4-1/Project/db/TOP.rtlv_sg.cdb
Example-b4-1/Project/db/TOP.rtlv_sg_swap.cdb
Example-b4-1/Project/db/TOP.sgdiff.cdb
Example-b4-1/Project/db/TOP.sgdiff.hdb
Example-b4-1/Project/db/TOP.sim.cvwf
Example-b4-1/Project/db/TOP.sim.hdb
Example-b4-1/Project/db/TOP.sim.qmsg
Example-b4-1/Project/db/TOP.sim.rdb
Example-b4-1/Project/db/TOP.sld_design_entry.sci
Example-b4-1/Project/db/TOP.sld_design_entry_dsc.sci
Example-b4-1/Project/db/TOP.smart_action.txt
Example-b4-1/Project/db/TOP.syn_hier_info
Example-b4-1/Project/db/TOP.tan.qmsg
Example-b4-1/Project/db/TOP.tis_db_list.ddb
Example-b4-1/Project/db/wed.wsf
Example-b4-1/Project/DualPortRAM.bsf
Example-b4-1/Project/DualPortRAM.v
Example-b4-1/Project/incremental_db/
Example-b4-1/Project/incremental_db/compiled_partitions/
Example-b4-1/Project/incremental_db/compiled_partitions/TOP.root_partition.map.kpt
Example-b4-1/Project/incremental_db/README
Example-b4-1/Project/Simulation/
Example-b4-1/Project/Simulation/altera_mf.v
Example-b4-1/Project/Simulation/DualPortRAM.v
Example-b4-1/Project/Simulation/modelsim.ini
Example-b4-1/Project/Simulation/sim.do
Example-b4-1/Project/Simulation/TOP.v
Example-b4-1/Project/Simulation/TOP.vt
Example-b4-1/Project/Simulation/vsim.wlf
Example-b4-1/Project/Simulation/wave.do
Example-b4-1/Project/Simulation/work/
Example-b4-1/Project/Simulation/work/@a@l@t@e@r@a_@d@e@v@i@c@e_@f@a@m@i@l@i@e@s/
Example-b4-1/Project/Simulation/work/@a@l@t@e@r@a_@d@e@v@i@c@e_@f@a@m@i@l@i@e@s/verilog.prw
Example-b4-1/Project/Simulation/work/@a@l@t@e@r@a_@d@e@v@i@c@e_@f@a@m@i@l@i@e@s/verilog.psm
Example-b4-1/Project/Simulation/work/@a@l@t@e@r@a_@d@e@v@i@c@e_@f@a@m@i@l@i@e@s/_primary.dat
Example-b4-1/Project/Simulation/work/@a@l@t@e@r@a_@d@e@v@i@c@e_@f@a@m@i@l@i@e@s/_primary.dbs
Example-b4-1/Project/Simulation/work/@a@l@t@e@r@a_@d@e@v@i@c@e_@f@a@m@i@l@i@e@s/_primary.vhd
Example-b4-1/Project/Simulation/work/@dual@port@r@a@m/
Example-b4-1/Project/Simulation/work/@dual@port@r@a@m/verilog.prw
Example-b4-1/Project/Simulation/work/@dual@port@r@a@m/verilog.psm
Example-b4-1/Project/Simulation/work/@dual@port@r@a@m/_primary.dat
Example-b4-1/Project/Simulation/work/@dual@port@r@a@m/_primary.dbs
Example-b4-1/Project/Simulation/work/@dual@port@r@a@m/_primary.vhd
Example-b4-1/Project/Simulation/work/@m@f_pll_reg/
Example-b4-1/Project/Simulation/work/@m@f_pll_reg/verilog.prw
Example-b4-1/Project/Simulation/work/@m@f_pll_reg/verilog.psm
Example-b4-1/Project/Simulation/work/@m@f_pll_reg/_primary.dat
Example-b4-1/Project/Simulation/work/@m@f_pll_reg/_primary.dbs
Example-b4-1/Project/Simulation/work/@m@f_pll_reg/_primary.vhd
Example-b4-1/Project/Simulation/work/@m@f_ram7x20_syn/
Example-b4-1/Project/Simulation/work/@m@f_ram7x20_syn/verilog.prw
Example-b4-1/Project/Simulation/work/@m@f_ram7x20_syn/verilog.psm
Example-b4-1/Project/Simulation/work/@m@f_ram7x20_syn/_primary.dat
Example-b4-1/Project/Simulation/work/@m@f_ram7x20_syn/_primary.dbs
Example-b4-1/Project/Simulation/work/@m@f_ram7x20_syn/_primary.vhd
Example-b4-1/Project/Simulation/work/@m@f_stratixii_pll/
Example-b4-1/Project/Simulation/work/@m@f_stratixii_pll/verilog.prw
Example-b4-1/Project/Simulation/work/@m@f_stratixii_pll/verilog.psm
Example-b4-1/Project/Simulation/work/@m@f_stratixii_pll/_primary.dat
Example-b4-1/Project/Simulation/work/@m@f_stratixii_pll/_primary.dbs
Example-b4-1/Project/Simulation/work/@m@f_stratixii_pll/_primary.vhd
Example-b4-1/Project/Simulation/work/@m@f_stratix_pll/
Example-b4-1/Project/Simulation/work/@m@f_stratix_pll/verilog.prw
Example-b4-1/Project/Simulation/work/@m@f_stratix_pll/verilog.psm
Example-b4-1/Project/Sim

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