hdlsrc/optfir.v
hdlsrc/optfir_compile.do
hdlsrc/optfir_synplify.tcl
hdlsrc/optfir_tb.v
hdlsrc/optfir_tb_compile.do
hdlsrc/optfir_tb_sim.do
hdlsrc/opt_fir.cr.mti
hdlsrc/opt_fir.mpf
hdlsrc/vsim.wlf
hdlsrc/work/@_opt/vopt1gw2m5
hdlsrc/work/@_opt/vopt1yd4mm
hdlsrc/work/@_opt/vopt40iyk5
hdlsrc/work/@_opt/vopt8g7vk5
hdlsrc/work/@_opt/voptbg1r44
hdlsrc/work/@_opt/voptf0qm44
hdlsrc/work/@_opt/voptjdjh5q
hdlsrc/work/@_opt/voptnx8e5q
hdlsrc/work/@_opt/vopttdyb5q
hdlsrc/work/@_opt/voptxxj85q
hdlsrc/work/@_opt/voptxz65m5
hdlsrc/work/@_opt/_deps
hdlsrc/work/optfir/verilog.asm
hdlsrc/work/optfir/verilog.rw
hdlsrc/work/optfir/_primary.dat
hdlsrc/work/optfir/_primary.dbs
hdlsrc/work/optfir/_primary.vhd
hdlsrc/work/optfir_tb/verilog.asm
hdlsrc/work/optfir_tb/verilog.rw
hdlsrc/work/optfir_tb/_primary.dat
hdlsrc/work/optfir_tb/_primary.dbs
hdlsrc/work/optfir_tb/_primary.vhd
hdlsrc/work/_info
hdlsrc/work/_vmake
untitled.fda
hdlsrc/work/@_opt
hdlsrc/work/optfir
hdlsrc/work/optfir_tb
hdlsrc/work/_temp
hdlsrc/work
hdlsrc