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文件名称:verilog-code

  • 所属分类：
    VHDL-FPGA-Verilog
  • 标签属性：
    [WORD]
  • 上传时间：
    2012-11-16
  • 文件大小：
    2.33mb
  • 已下载：
    0次
  • 提 供 者：
    pon***
  • 相关连接：
    无
  • 下载说明：
    别用迅雷下载，失败请重下，重下不扣分！
修正介绍说明

介绍说明－－下载内容来自于网络，使用问题请自行百度

都是verilog代码：多路选择器代码，储存器代码，时钟分频器代码，串并转换电路代码，香农扩展运算代码，ram代码。-MUX code and REGISTER code clock divider code string conversion circuit code, Shannon extended op code, the ram code.
(系统自动生成,下载前可以参看下载内容)

下载文件列表

verilog code/
verilog code/CRC10.v
verilog code/Example-2-1/
verilog code/Example-2-1/HelloVlog.v
verilog code/Example-3-1/
verilog code/Example-3-1/FullAdd.v
verilog code/Example-3-1/transcript
verilog code/Example-3-2/
verilog code/Example-3-2/FullAdd.v
verilog code/Example-3-3/
verilog code/Example-3-3/CRC10.v
verilog code/Example-4-1/
verilog code/Example-4-10/
verilog code/Example-4-10/bibus/
verilog code/Example-4-10/bibus/bibus.prd
verilog code/Example-4-10/bibus/bibus.prj
verilog code/Example-4-10/bibus/bibus.v
verilog code/Example-4-10/bibus/decode.v
verilog code/Example-4-10/bibus/rev_1/
verilog code/Example-4-10/bibus/rev_1/bibus.fse
verilog code/Example-4-10/bibus/rev_1/bibus.srd
verilog code/Example-4-10/bibus/rev_1/bibus.srm
verilog code/Example-4-10/bibus/rev_1/bibus.srr
verilog code/Example-4-10/bibus/rev_1/bibus.srs
verilog code/Example-4-10/bibus/rev_1/bibus.sxr
verilog code/Example-4-10/bibus/rev_1/bibus.tcl
verilog code/Example-4-10/bibus/rev_1/bibus.tlg
verilog code/Example-4-10/bibus/rev_1/bibus.vqm
verilog code/Example-4-10/bibus/rev_1/bibus.xrf
verilog code/Example-4-10/bibus/rev_1/bibus_cons.tcl
verilog code/Example-4-10/bibus/rev_1/bibus_rm.tcl
verilog code/Example-4-10/bibus/rev_1/rpt_bibus.areasrr
verilog code/Example-4-10/bibus/rev_1/rpt_bibus_areasrr.htm
verilog code/Example-4-10/bibus/rev_1/syntmp/
verilog code/Example-4-10/bibus/rev_1/syntmp/bibus.msg
verilog code/Example-4-10/bibus/rev_1/syntmp/bibus.plg
verilog code/Example-4-10/bibus/rev_1/syntmp/bibus_cons_ui.tcl
verilog code/Example-4-10/bibus/rev_1/verif/
verilog code/Example-4-10/bibus/rev_1/verif/bibus.vif
verilog code/Example-4-10/bibus/syntmp.msg
verilog code/Example-4-10/complex_bibus/
verilog code/Example-4-10/complex_bibus/complex_bibus.prd
verilog code/Example-4-10/complex_bibus/complex_bibus.prj
verilog code/Example-4-10/complex_bibus/complex_bibus.v
verilog code/Example-4-10/complex_bibus/complex_bibus2.v
verilog code/Example-4-10/complex_bibus/counter.v
verilog code/Example-4-10/complex_bibus/decode.v
verilog code/Example-4-10/complex_bibus/rev_1/
verilog code/Example-4-10/complex_bibus/rev_1/AutoConstraint_complex_bibus.sdc
verilog code/Example-4-10/complex_bibus/rev_1/complex_bibus.fse
verilog code/Example-4-10/complex_bibus/rev_1/complex_bibus.srd
verilog code/Example-4-10/complex_bibus/rev_1/complex_bibus.srm
verilog code/Example-4-10/complex_bibus/rev_1/complex_bibus.srr
verilog code/Example-4-10/complex_bibus/rev_1/complex_bibus.srs
verilog code/Example-4-10/complex_bibus/rev_1/complex_bibus.sxr
verilog code/Example-4-10/complex_bibus/rev_1/complex_bibus.tcl
verilog code/Example-4-10/complex_bibus/rev_1/complex_bibus.tlg
verilog code/Example-4-10/complex_bibus/rev_1/complex_bibus.vqm
verilog code/Example-4-10/complex_bibus/rev_1/complex_bibus.xrf
verilog code/Example-4-10/complex_bibus/rev_1/complex_bibus2.fse
verilog code/Example-4-10/complex_bibus/rev_1/complex_bibus2.srd
verilog code/Example-4-10/complex_bibus/rev_1/complex_bibus2.srm
verilog code/Example-4-10/complex_bibus/rev_1/complex_bibus2.srr
verilog code/Example-4-10/complex_bibus/rev_1/complex_bibus2.srs
verilog code/Example-4-10/complex_bibus/rev_1/complex_bibus2.sxr
verilog code/Example-4-10/complex_bibus/rev_1/complex_bibus2.tcl
verilog code/Example-4-10/complex_bibus/rev_1/complex_bibus2.tlg
verilog code/Example-4-10/complex_bibus/rev_1/complex_bibus2.vqm
verilog code/Example-4-10/complex_bibus/rev_1/complex_bibus2.xrf
verilog code/Example-4-10/complex_bibus/rev_1/complex_bibus2_cons.tcl
verilog code/Example-4-10/complex_bibus/rev_1/complex_bibus2_rm.tcl
verilog code/Example-4-10/complex_bibus/rev_1/complex_bibus_cons.tcl
verilog code/Example-4-10/complex_bibus/rev_1/complex_bibus_rm.tcl
verilog code/Example-4-10/complex_bibus/rev_1/decode.srr
verilog code/Example-4-10/complex_bibus/rev_1/par_1/
verilog code/Example-4-10/complex_bibus/rev_1/rpt_complex_bibus.areasrr
verilog code/Example-4-10/complex_bibus/rev_1/rpt_complex_bibus_areasrr.htm
verilog code/Example-4-10/complex_bibus/rev_1/syntmp/
verilog code/Example-4-10/complex_bibus/rev_1/syntmp/complex_bibus.msg
verilog code/Example-4-10/complex_bibus/rev_1/syntmp/complex_bibus.plg
verilog code/Example-4-10/complex_bibus/rev_1/syntmp/complex_bibus2.plg
verilog code/Example-4-10/complex_bibus/rev_1/syntmp/complex_bibus2_cons_ui.tcl
verilog code/Example-4-10/complex_bibus/rev_1/syntmp/complex_bibus_cons_ui.tcl
verilog code/Example-4-10/complex_bibus/rev_1/verif/
verilog code/Example-4-10/complex_bibus/rev_1/verif/complex_bibus.vif
verilog code/Example-4-10/complex_bibus/rev_1/verif/complex_bibus2.vif
verilog code/Example-4-10/complex_bibus/syntmp.msg
verilog code/Example-4-10/source/
verilog code/Example-4-10/source/bibus.v
verilog code/Example-4-10/source/complex_bibus.v
verilog code/Example-4-10/source/complex_bibus2.v
verilog code/Example-4-10/source/counter.v
verilog code/Example-4-10/source/decode.v
verilog code/Example-4-10/示例说明.doc
verilog code/Example-4-11/
verilog code/Example-4-11/mux.prd
verilog code/Example-4-11/mux.prj
verilog code/Example-4-11/mux.v
verilog code/Example-4-11/mux2.v
verilog cod

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