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文件名称:music_player

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  • 上传时间:
    2012-11-16
  • 文件大小:
    5.14mb
  • 已下载:
    0次
  • 提 供 者:
  • 相关连接:
  • 下载说明:
    别用迅雷下载,失败请重下,重下不扣分!

介绍说明--下载内容来自于网络,使用问题请自行百度

用verilog编写的音乐播放器,内置3首歌-Music player written in Verilog, built-in 3-song
(系统自动生成,下载前可以参看下载内容)

下载文件列表

lab28_new/PipelineCPU/ISE/DataRAM.mif
lab28_new/PipelineCPU/ISE/DataRAM.ngc
lab28_new/PipelineCPU/ISE/DataRAM.sym
lab28_new/PipelineCPU/ISE/DataRAM.v
lab28_new/PipelineCPU/ISE/DataRAM.veo
lab28_new/PipelineCPU/ISE/DataRAM.vhd
lab28_new/PipelineCPU/ISE/DataRAM.vho
lab28_new/PipelineCPU/ISE/DataRAM.xco
lab28_new/PipelineCPU/ISE/DataRAM_flist.txt
lab28_new/PipelineCPU/ISE/DataRAM_readme.txt
lab28_new/PipelineCPU/ISE/DataRAM_xmdf.tcl
lab28_new/PipelineCPU/ISE/MipsPipelineCPU.bld
lab28_new/PipelineCPU/ISE/MipsPipelineCPU.cmd_log
lab28_new/PipelineCPU/ISE/MipsPipelineCPU.ise
lab28_new/PipelineCPU/ISE/MipsPipelineCPU.ise_ISE_Backup
lab28_new/PipelineCPU/ISE/MipsPipelineCPU.lso
lab28_new/PipelineCPU/ISE/MipsPipelineCPU.ncd
lab28_new/PipelineCPU/ISE/MipsPipelineCPU.ngc
lab28_new/PipelineCPU/ISE/MipsPipelineCPU.ngd
lab28_new/PipelineCPU/ISE/MipsPipelineCPU.ngr
lab28_new/PipelineCPU/ISE/MipsPipelineCPU.ntrc_log
lab28_new/PipelineCPU/ISE/MipsPipelineCPU.pad
lab28_new/PipelineCPU/ISE/MipsPipelineCPU.par
lab28_new/PipelineCPU/ISE/MipsPipelineCPU.pcf
lab28_new/PipelineCPU/ISE/MipsPipelineCPU.prj
lab28_new/PipelineCPU/ISE/MipsPipelineCPU.restore
lab28_new/PipelineCPU/ISE/MipsPipelineCPU.spl
lab28_new/PipelineCPU/ISE/MipsPipelineCPU.stx
lab28_new/PipelineCPU/ISE/MipsPipelineCPU.sym
lab28_new/PipelineCPU/ISE/MipsPipelineCPU.syr
lab28_new/PipelineCPU/ISE/mipspipelinecpu.twr
lab28_new/PipelineCPU/ISE/mipspipelinecpu.twx
lab28_new/PipelineCPU/ISE/MipsPipelineCPU.unroutes
lab28_new/PipelineCPU/ISE/MipsPipelineCPU.xpi
lab28_new/PipelineCPU/ISE/MipsPipelineCPU.xst
lab28_new/PipelineCPU/ISE/MipsPipelineCPU_guide.ncd
lab28_new/PipelineCPU/ISE/MipsPipelineCPU_map.map
lab28_new/PipelineCPU/ISE/MipsPipelineCPU_map.mrp
lab28_new/PipelineCPU/ISE/MipsPipelineCPU_map.ncd
lab28_new/PipelineCPU/ISE/MipsPipelineCPU_map.ngm
lab28_new/PipelineCPU/ISE/MipsPipelineCPU_pad.csv
lab28_new/PipelineCPU/ISE/MipsPipelineCPU_pad.txt
lab28_new/PipelineCPU/ISE/MipsPipelineCPU_prev_built.ngd
lab28_new/PipelineCPU/ISE/MipsPipelineCPU_summary.html
lab28_new/PipelineCPU/ISE/MipsPipelineCPU_summary.xml
lab28_new/PipelineCPU/ISE/MipsPipelineCPU_usage.xml
lab28_new/PipelineCPU/ISE/xst/dump.xst/MipsPipelineCPU.prj/ntrc.scr
lab28_new/PipelineCPU/ISE/xst/work/hdllib.ref
lab28_new/PipelineCPU/ISE/xst/work/vlg07/add__32bits.bin
lab28_new/PipelineCPU/ISE/xst/work/vlg07/dffre.bin
lab28_new/PipelineCPU/ISE/xst/work/vlg1E/_data_r_a_m.bin
lab28_new/PipelineCPU/ISE/xst/work/vlg28/dff.bin
lab28_new/PipelineCPU/ISE/xst/work/vlg28/_a_l_u__tb__v.bin
lab28_new/PipelineCPU/ISE/xst/work/vlg2A/_a_l_u.bin
lab28_new/PipelineCPU/ISE/xst/work/vlg2F/_mips_pipeline_c_p_u.bin
lab28_new/PipelineCPU/ISE/xst/work/vlg30/_decode.bin
lab28_new/PipelineCPU/ISE/xst/work/vlg31/_e_x.bin
lab28_new/PipelineCPU/ISE/xst/work/vlg31/_i_d.bin
lab28_new/PipelineCPU/ISE/xst/work/vlg33/_i_f.bin
lab28_new/PipelineCPU/ISE/xst/work/vlg3A/dffr.bin
lab28_new/PipelineCPU/ISE/xst/work/vlg49/add__4bits__optical.bin
lab28_new/PipelineCPU/ISE/xst/work/vlg4A/add__4bits.bin
lab28_new/PipelineCPU/ISE/xst/work/vlg73/_multi_registers.bin
lab28_new/PipelineCPU/ISE/xst/work/vlg7C/_instruction_r_o_m.bin
lab28_new/PipelineCPU/ISE/_ngo/netlist.lst
lab28_new/PipelineCPU/ISE/_xmsgs/map.xmsgs
lab28_new/PipelineCPU/ISE/_xmsgs/ngdbuild.xmsgs
lab28_new/PipelineCPU/ISE/_xmsgs/par.xmsgs
lab28_new/PipelineCPU/ISE/_xmsgs/trce.xmsgs
lab28_new/PipelineCPU/ISE/_xmsgs/xst.xmsgs
lab28_new/PipelineCPU/SIM/addr.vhd
lab28_new/PipelineCPU/SIM/add_32bits.vhd
lab28_new/PipelineCPU/SIM/add_32bits.vhd.bak
lab28_new/PipelineCPU/SIM/ALU/ALU_tb.v
lab28_new/PipelineCPU/SIM/ALU/ALU_tb2.v
lab28_new/PipelineCPU/SIM/alu.cr.mti
lab28_new/PipelineCPU/SIM/alu.mpf
lab28_new/PipelineCPU/SIM/DataRAM.mif
lab28_new/PipelineCPU/SIM/Decode/Decode_tb.v
lab28_new/PipelineCPU/SIM/Decode/Decode_tb.v.bak
lab28_new/PipelineCPU/SIM/IF/IF_tb.v
lab28_new/PipelineCPU/SIM/modelsim.ini
lab28_new/PipelineCPU/SIM/top/top_tb.v
lab28_new/PipelineCPU/SIM/top_tb.v
lab28_new/PipelineCPU/SIM/vsim.wlf
lab28_new/PipelineCPU/SIM/wlft2x6zxj
lab28_new/PipelineCPU/SIM/wlftwjft9m
lab28_new/PipelineCPU/SIM/work/@a@l@u/_primary.dat
lab28_new/PipelineCPU/SIM/work/@a@l@u/_primary.dbs
lab28_new/PipelineCPU/SIM/work/@a@l@u/_primary.vhd
lab28_new/PipelineCPU/SIM/work/@a@l@u_tb_v/_primary.dat
lab28_new/PipelineCPU/SIM/work/@a@l@u_tb_v/_primary.dbs
lab28_new/PipelineCPU/SIM/work/@a@l@u_tb_v/_primary.vhd
lab28_new/PipelineCPU/SIM/work/@data@r@a@m/_primary.dat
lab28_new/PipelineCPU/SIM/work/@data@r@a@m/_primary.dbs
lab28_new/PipelineCPU/SIM/work/@data@r@a@m/_primary.vhd
lab28_new/PipelineCPU/SIM/work/@decode/_primary.dat
lab28_new/PipelineCPU/SIM/work/@decode/_primary.dbs
lab28_new/PipelineCPU/SIM/work/@decode/_primary.vhd
lab28_new/PipelineCPU/SIM/work/@decode_tb_v/_primary.dat
lab28_new/PipelineCPU/SIM/work/@decode_tb_v/_primary.dbs
lab28_new/PipelineCPU/SIM/work/@decode_tb_v/_primary.vhd
lab28_new/PipelineCPU/SIM/work/@e@x/_primary.dat
lab28_new/PipelineCPU/SIM/work/@e@x/_primary.dbs
lab28_new/PipelineCPU/SIM/work/@e@x/_primary.vhd
lab28_new/PipelineCPU/SIM/work/@i@d/_primary.dat
lab28_new/PipelineCPU/SIM/work/@i@d/_pri

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