文件名称:project9_freq_counter
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- 上传时间:2012-11-16
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文件大小:3.63mb
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数字频率计的设计,基于VERILOG的数字频率计的设计-Digital frequency plan design, based on the number of VERILOG frequency meter design
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下载文件列表
project9_freq_counter/clk_gen.v
project9_freq_counter/CONT_10.v
project9_freq_counter/FPGA应用开发项目_9.ppt
project9_freq_counter/Freq_counter.pdf
project9_freq_counter/Freq_counter.v
project9_freq_counter/Freq_counter_LCD.sof
project9_freq_counter/Freq_pin.csv
project9_freq_counter/LCD_1602.pdf
project9_freq_counter/LCD_1602.v
project9_freq_counter/PLL50M.ppf
project9_freq_counter/PLL50M.v
project9_freq_counter/SEG7_LUT.v
project9_freq_counter/sem_drive.v
project9_freq_counter
project9_freq_counter/CONT_10.v
project9_freq_counter/FPGA应用开发项目_9.ppt
project9_freq_counter/Freq_counter.pdf
project9_freq_counter/Freq_counter.v
project9_freq_counter/Freq_counter_LCD.sof
project9_freq_counter/Freq_pin.csv
project9_freq_counter/LCD_1602.pdf
project9_freq_counter/LCD_1602.v
project9_freq_counter/PLL50M.ppf
project9_freq_counter/PLL50M.v
project9_freq_counter/SEG7_LUT.v
project9_freq_counter/sem_drive.v
project9_freq_counter
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