文件名称:uart2bus_latest
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- 上传时间:2012-11-16
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文件大小:1.15mb
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用于fpga并口连接的工程哈,请大家支持一下-For fpga parallel port connection works Kazakhstan, support for what
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下载文件列表
uart2bus_latest/bcb/CLAIR.JPG
uart2bus_latest/bcb/MainDlg.cpp
uart2bus_latest/bcb/MainDlg.ddp
uart2bus_latest/bcb/MainDlg.dfm
uart2bus_latest/bcb/MainDlg.h
uart2bus_latest/bcb/MainDlg.obj
uart2bus_latest/bcb/MainDlg.~cpp
uart2bus_latest/bcb/MainDlg.~ddp
uart2bus_latest/bcb/MainDlg.~dfm
uart2bus_latest/bcb/MainDlg.~h
uart2bus_latest/bcb/pc_uart.c
uart2bus_latest/bcb/pc_uart.~c
uart2bus_latest/bcb/spcomm.rar
uart2bus_latest/bcb/STR_U2B.bpr
uart2bus_latest/bcb/STR_U2B.cpp
uart2bus_latest/bcb/STR_U2B.exe
uart2bus_latest/bcb/STR_U2B.obj
uart2bus_latest/bcb/STR_U2B.res
uart2bus_latest/bcb/STR_U2B.tds
uart2bus_latest/bcb/STR_U2B.~bpr
uart2bus_latest/bcb/STR_U2B.~cpp
uart2bus_latest/bcb/片段.shs
uart2bus_latest/uart2bus/trunk/doc/UART to Bus Core Specifications.pdf
uart2bus_latest/uart2bus/trunk/QUARTUS2/PLL.ppf
uart2bus_latest/uart2bus/trunk/QUARTUS2/PLL.qip
uart2bus_latest/uart2bus/trunk/QUARTUS2/PLL.v
uart2bus_latest/uart2bus/trunk/QUARTUS2/PLL_wave0.jpg
uart2bus_latest/uart2bus/trunk/QUARTUS2/PLL_waveforms.html
uart2bus_latest/uart2bus/trunk/QUARTUS2/starter_src/fpga_starter_pin.tcl
uart2bus_latest/uart2bus/trunk/QUARTUS2/starter_src/fpga_starter_pin.tcl.bak
uart2bus_latest/uart2bus/trunk/QUARTUS2/starter_src/m_dynamic_seg7.v
uart2bus_latest/uart2bus/trunk/QUARTUS2/starter_src/starter_uart2bus.v
uart2bus_latest/uart2bus/trunk/QUARTUS2/starter_src/starter_uart2bus.v.bak
uart2bus_latest/uart2bus/trunk/QUARTUS2/starter_uart2bus.asm.rpt
uart2bus_latest/uart2bus/trunk/QUARTUS2/starter_uart2bus.cdf
uart2bus_latest/uart2bus/trunk/QUARTUS2/starter_uart2bus.done
uart2bus_latest/uart2bus/trunk/QUARTUS2/starter_uart2bus.dpf
uart2bus_latest/uart2bus/trunk/QUARTUS2/starter_uart2bus.fit.rpt
uart2bus_latest/uart2bus/trunk/QUARTUS2/starter_uart2bus.fit.smsg
uart2bus_latest/uart2bus/trunk/QUARTUS2/starter_uart2bus.fit.summary
uart2bus_latest/uart2bus/trunk/QUARTUS2/starter_uart2bus.flow.rpt
uart2bus_latest/uart2bus/trunk/QUARTUS2/starter_uart2bus.map.rpt
uart2bus_latest/uart2bus/trunk/QUARTUS2/starter_uart2bus.map.summary
uart2bus_latest/uart2bus/trunk/QUARTUS2/starter_uart2bus.pin
uart2bus_latest/uart2bus/trunk/QUARTUS2/starter_uart2bus.pof
uart2bus_latest/uart2bus/trunk/QUARTUS2/starter_uart2bus.qpf
uart2bus_latest/uart2bus/trunk/QUARTUS2/starter_uart2bus.qsf
uart2bus_latest/uart2bus/trunk/QUARTUS2/starter_uart2bus.qws
uart2bus_latest/uart2bus/trunk/QUARTUS2/starter_uart2bus.sof
uart2bus_latest/uart2bus/trunk/QUARTUS2/starter_uart2bus.tan.rpt
uart2bus_latest/uart2bus/trunk/QUARTUS2/starter_uart2bus.tan.summary
uart2bus_latest/uart2bus/trunk/QUARTUS2/starter_uart2bus_description.txt
uart2bus_latest/uart2bus/trunk/scilab/calc_baud_gen.sce
uart2bus_latest/uart2bus/trunk/verilog/bench/reg_file_model.v
uart2bus_latest/uart2bus/trunk/verilog/bench/tb_bin_uart2bus_top.v
uart2bus_latest/uart2bus/trunk/verilog/bench/tb_txt_uart2bus_top.v
uart2bus_latest/uart2bus/trunk/verilog/bench/tb_uart2bus_top.v
uart2bus_latest/uart2bus/trunk/verilog/bench/timescale.v
uart2bus_latest/uart2bus/trunk/verilog/bench/uart_tasks.v
uart2bus_latest/uart2bus/trunk/verilog/rtl/baud_gen.v
uart2bus_latest/uart2bus/trunk/verilog/rtl/uart2bus_top.v
uart2bus_latest/uart2bus/trunk/verilog/rtl/uart_parser.v
uart2bus_latest/uart2bus/trunk/verilog/rtl/uart_rx.v
uart2bus_latest/uart2bus/trunk/verilog/rtl/uart_top.v
uart2bus_latest/uart2bus/trunk/verilog/rtl/uart_tx.v
uart2bus_latest/uart2bus/trunk/verilog/sim/icarus/block_bin.cfg
uart2bus_latest/uart2bus/trunk/verilog/sim/icarus/block_txt.cfg
uart2bus_latest/uart2bus/trunk/verilog/sim/icarus/compile_bin.bat
uart2bus_latest/uart2bus/trunk/verilog/sim/icarus/compile_txt.bat
uart2bus_latest/uart2bus/trunk/verilog/sim/icarus/gtk.bat
uart2bus_latest/uart2bus/trunk/verilog/sim/icarus/run.bat
uart2bus_latest/uart2bus/trunk/verilog/sim/icarus/test.bin
uart2bus_latest/uart2bus/trunk/verilog/sim/icarus/test.txt
uart2bus_latest/uart2bus/trunk/verilog/syn/altera/uart2bus.qpf
uart2bus_latest/uart2bus/trunk/verilog/syn/altera/uart2bus.qws
uart2bus_latest/uart2bus/trunk/verilog/syn/altera/uart2bus_top.qsf
uart2bus_latest/uart2bus/trunk/verilog/syn/xilinx/uart2bus.xise
uart2bus_latest/uart2bus/trunk/vhdl/bench/regFileModel.vhd
uart2bus_latest/uart2bus/trunk/vhdl/bench/uart2BusTop_bin_tb.vhd
uart2bus_latest/uart2bus/trunk/vhdl/bench/uart2BusTop_txt_tb.vhd
uart2bus_latest/uart2bus/trunk/vhdl/rtl/baudGen.vhd
uart2bus_latest/uart2bus/trunk/vhdl/rtl/uart2BusTop.vhd
uart2bus_latest/uart2bus/trunk/vhdl/rtl/uartParser.vhd
uart2bus_latest/uart2bus/trunk/vhdl/rtl/uartRx.vhd
uart2bus_latest/uart2bus/trunk/vhdl/rtl/uartTop.vhd
uart2bus_latest/uart2bus/trunk/vhdl/rtl/uartTx.vhd
uart2bus_latest/uart2bus/trunk/vhdl/syn/xilinx/uart2bus.xise
uart2bus_latest/uart2bus/trunk/vhdl/test.bin
uart2bus_latest/uart2bus/trunk/vhdl/test.txt
uart2bus_latest/uart2bus/trunk/verilog/sim/icarus
uart2bus_latest/uart2bus/trunk/verilog/syn/altera
uart2bus_latest/uart2bus/trunk/verilog/syn/xilinx
uart2bus_latest/uart2bus/trunk/vhdl/sim/modelsim
uart2bus_latest/uart2bus/trunk/vhdl/syn/xilinx
uart2bus_latest/uart2bus/trunk/QUARTUS2/starter_src
uart2bus_latest/uart2bus/trunk/verilog/bench
ua
uart2bus_latest/bcb/MainDlg.cpp
uart2bus_latest/bcb/MainDlg.ddp
uart2bus_latest/bcb/MainDlg.dfm
uart2bus_latest/bcb/MainDlg.h
uart2bus_latest/bcb/MainDlg.obj
uart2bus_latest/bcb/MainDlg.~cpp
uart2bus_latest/bcb/MainDlg.~ddp
uart2bus_latest/bcb/MainDlg.~dfm
uart2bus_latest/bcb/MainDlg.~h
uart2bus_latest/bcb/pc_uart.c
uart2bus_latest/bcb/pc_uart.~c
uart2bus_latest/bcb/spcomm.rar
uart2bus_latest/bcb/STR_U2B.bpr
uart2bus_latest/bcb/STR_U2B.cpp
uart2bus_latest/bcb/STR_U2B.exe
uart2bus_latest/bcb/STR_U2B.obj
uart2bus_latest/bcb/STR_U2B.res
uart2bus_latest/bcb/STR_U2B.tds
uart2bus_latest/bcb/STR_U2B.~bpr
uart2bus_latest/bcb/STR_U2B.~cpp
uart2bus_latest/bcb/片段.shs
uart2bus_latest/uart2bus/trunk/doc/UART to Bus Core Specifications.pdf
uart2bus_latest/uart2bus/trunk/QUARTUS2/PLL.ppf
uart2bus_latest/uart2bus/trunk/QUARTUS2/PLL.qip
uart2bus_latest/uart2bus/trunk/QUARTUS2/PLL.v
uart2bus_latest/uart2bus/trunk/QUARTUS2/PLL_wave0.jpg
uart2bus_latest/uart2bus/trunk/QUARTUS2/PLL_waveforms.html
uart2bus_latest/uart2bus/trunk/QUARTUS2/starter_src/fpga_starter_pin.tcl
uart2bus_latest/uart2bus/trunk/QUARTUS2/starter_src/fpga_starter_pin.tcl.bak
uart2bus_latest/uart2bus/trunk/QUARTUS2/starter_src/m_dynamic_seg7.v
uart2bus_latest/uart2bus/trunk/QUARTUS2/starter_src/starter_uart2bus.v
uart2bus_latest/uart2bus/trunk/QUARTUS2/starter_src/starter_uart2bus.v.bak
uart2bus_latest/uart2bus/trunk/QUARTUS2/starter_uart2bus.asm.rpt
uart2bus_latest/uart2bus/trunk/QUARTUS2/starter_uart2bus.cdf
uart2bus_latest/uart2bus/trunk/QUARTUS2/starter_uart2bus.done
uart2bus_latest/uart2bus/trunk/QUARTUS2/starter_uart2bus.dpf
uart2bus_latest/uart2bus/trunk/QUARTUS2/starter_uart2bus.fit.rpt
uart2bus_latest/uart2bus/trunk/QUARTUS2/starter_uart2bus.fit.smsg
uart2bus_latest/uart2bus/trunk/QUARTUS2/starter_uart2bus.fit.summary
uart2bus_latest/uart2bus/trunk/QUARTUS2/starter_uart2bus.flow.rpt
uart2bus_latest/uart2bus/trunk/QUARTUS2/starter_uart2bus.map.rpt
uart2bus_latest/uart2bus/trunk/QUARTUS2/starter_uart2bus.map.summary
uart2bus_latest/uart2bus/trunk/QUARTUS2/starter_uart2bus.pin
uart2bus_latest/uart2bus/trunk/QUARTUS2/starter_uart2bus.pof
uart2bus_latest/uart2bus/trunk/QUARTUS2/starter_uart2bus.qpf
uart2bus_latest/uart2bus/trunk/QUARTUS2/starter_uart2bus.qsf
uart2bus_latest/uart2bus/trunk/QUARTUS2/starter_uart2bus.qws
uart2bus_latest/uart2bus/trunk/QUARTUS2/starter_uart2bus.sof
uart2bus_latest/uart2bus/trunk/QUARTUS2/starter_uart2bus.tan.rpt
uart2bus_latest/uart2bus/trunk/QUARTUS2/starter_uart2bus.tan.summary
uart2bus_latest/uart2bus/trunk/QUARTUS2/starter_uart2bus_description.txt
uart2bus_latest/uart2bus/trunk/scilab/calc_baud_gen.sce
uart2bus_latest/uart2bus/trunk/verilog/bench/reg_file_model.v
uart2bus_latest/uart2bus/trunk/verilog/bench/tb_bin_uart2bus_top.v
uart2bus_latest/uart2bus/trunk/verilog/bench/tb_txt_uart2bus_top.v
uart2bus_latest/uart2bus/trunk/verilog/bench/tb_uart2bus_top.v
uart2bus_latest/uart2bus/trunk/verilog/bench/timescale.v
uart2bus_latest/uart2bus/trunk/verilog/bench/uart_tasks.v
uart2bus_latest/uart2bus/trunk/verilog/rtl/baud_gen.v
uart2bus_latest/uart2bus/trunk/verilog/rtl/uart2bus_top.v
uart2bus_latest/uart2bus/trunk/verilog/rtl/uart_parser.v
uart2bus_latest/uart2bus/trunk/verilog/rtl/uart_rx.v
uart2bus_latest/uart2bus/trunk/verilog/rtl/uart_top.v
uart2bus_latest/uart2bus/trunk/verilog/rtl/uart_tx.v
uart2bus_latest/uart2bus/trunk/verilog/sim/icarus/block_bin.cfg
uart2bus_latest/uart2bus/trunk/verilog/sim/icarus/block_txt.cfg
uart2bus_latest/uart2bus/trunk/verilog/sim/icarus/compile_bin.bat
uart2bus_latest/uart2bus/trunk/verilog/sim/icarus/compile_txt.bat
uart2bus_latest/uart2bus/trunk/verilog/sim/icarus/gtk.bat
uart2bus_latest/uart2bus/trunk/verilog/sim/icarus/run.bat
uart2bus_latest/uart2bus/trunk/verilog/sim/icarus/test.bin
uart2bus_latest/uart2bus/trunk/verilog/sim/icarus/test.txt
uart2bus_latest/uart2bus/trunk/verilog/syn/altera/uart2bus.qpf
uart2bus_latest/uart2bus/trunk/verilog/syn/altera/uart2bus.qws
uart2bus_latest/uart2bus/trunk/verilog/syn/altera/uart2bus_top.qsf
uart2bus_latest/uart2bus/trunk/verilog/syn/xilinx/uart2bus.xise
uart2bus_latest/uart2bus/trunk/vhdl/bench/regFileModel.vhd
uart2bus_latest/uart2bus/trunk/vhdl/bench/uart2BusTop_bin_tb.vhd
uart2bus_latest/uart2bus/trunk/vhdl/bench/uart2BusTop_txt_tb.vhd
uart2bus_latest/uart2bus/trunk/vhdl/rtl/baudGen.vhd
uart2bus_latest/uart2bus/trunk/vhdl/rtl/uart2BusTop.vhd
uart2bus_latest/uart2bus/trunk/vhdl/rtl/uartParser.vhd
uart2bus_latest/uart2bus/trunk/vhdl/rtl/uartRx.vhd
uart2bus_latest/uart2bus/trunk/vhdl/rtl/uartTop.vhd
uart2bus_latest/uart2bus/trunk/vhdl/rtl/uartTx.vhd
uart2bus_latest/uart2bus/trunk/vhdl/syn/xilinx/uart2bus.xise
uart2bus_latest/uart2bus/trunk/vhdl/test.bin
uart2bus_latest/uart2bus/trunk/vhdl/test.txt
uart2bus_latest/uart2bus/trunk/verilog/sim/icarus
uart2bus_latest/uart2bus/trunk/verilog/syn/altera
uart2bus_latest/uart2bus/trunk/verilog/syn/xilinx
uart2bus_latest/uart2bus/trunk/vhdl/sim/modelsim
uart2bus_latest/uart2bus/trunk/vhdl/syn/xilinx
uart2bus_latest/uart2bus/trunk/QUARTUS2/starter_src
uart2bus_latest/uart2bus/trunk/verilog/bench
ua
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