文件名称:1_061026140305
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基于FPGA的I2C总线模拟，采用verilog HDL语言编写。- Based on the FPGA I2C main line simulation, uses verilog the HDL language compilation.-FPGA-based I2C bus simulation, using verilog HDL language. - Based on the FPGA I2C main line simulation, verilog uses the HDL language compilation.
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下载文件列表
RD1006/Document/rd1006.pdf
RD1006/Document
RD1006/Source/i2c.v
RD1006/Source/i2c_clk.v
RD1006/Source/i2c_rreg.v
RD1006/Source/i2c_st.v
RD1006/Source/i2c_tbuf.v
RD1006/Source/i2c_wreg.v
RD1006/Source/transcript
RD1006/Source
RD1006/TestFixture/clk_rst.v
RD1006/TestFixture/i2c_slave.v
RD1006/TestFixture/i2c_tb.v
RD1006/TestFixture/micro.v
RD1006/TestFixture
RD1006
www.dssz.com.txt
RD1006/Document
RD1006/Source/i2c.v
RD1006/Source/i2c_clk.v
RD1006/Source/i2c_rreg.v
RD1006/Source/i2c_st.v
RD1006/Source/i2c_tbuf.v
RD1006/Source/i2c_wreg.v
RD1006/Source/transcript
RD1006/Source
RD1006/TestFixture/clk_rst.v
RD1006/TestFixture/i2c_slave.v
RD1006/TestFixture/i2c_tb.v
RD1006/TestFixture/micro.v
RD1006/TestFixture
RD1006
www.dssz.com.txt
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