在数字电路中，常需要对较高频率的时钟进行分频操作，得到较低频率的时钟信号。我们知道，在硬件电路设计中时钟信号时非常重要的。

下面我们介绍分频器的VHDL描述，在源代码中完成对时钟信号CLK的2分频，4分频，8分频，16分频。

-In digital circuits, and often need high frequency clock divider operating in lower frequency clock signal. We know that when the clock signal in the hardware circuit design is very important. Here we introduce the VHDL descr iption of the divider in the source code of the clock signal CLK divided by 2, 4 divider, divide by 8, divided by 16.