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文件名称:Xilinx-verilog

  • 所属分类：
    VHDL-FPGA-Verilog
  • 标签属性：
    [C/C++] [源码]
  • 上传时间：
    2012-11-16
  • 文件大小：
    11.39mb
  • 已下载：
    0次
  • 提 供 者：
    t****
  • 相关连接：
    无
  • 下载说明：
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修正介绍说明

介绍说明－－下载内容来自于网络，使用问题请自行百度

xilinx培训源码及工程文件,给予spartan 3E开发板的！希望对初学者有所帮助-Xilinx training codes and project！！

IT‘s worth to learn！！
(系统自动生成,下载前可以参看下载内容)

下载文件列表

verilog/
verilog/lab1/
verilog/lab1/Flow_lab/
verilog/lab1/Flow_lab/Flow_lab.gise
verilog/lab1/Flow_lab/Flow_lab.xise
verilog/lab1/Flow_lab/fuse.log
verilog/lab1/Flow_lab/fuse.xmsgs
verilog/lab1/Flow_lab/fuseRelaunch.cmd
verilog/lab1/Flow_lab/INT_TEST.V
verilog/lab1/Flow_lab/iseconfig/
verilog/lab1/Flow_lab/iseconfig/Flow_lab.projectmgr
verilog/lab1/Flow_lab/iseconfig/kcpsm3_int_test.xreport
verilog/lab1/Flow_lab/isim/
verilog/lab1/Flow_lab/isim.cmd
verilog/lab1/Flow_lab/isim.log
verilog/lab1/Flow_lab/isim/isim_usage_statistics.html
verilog/lab1/Flow_lab/isim/pn_info
verilog/lab1/Flow_lab/isim/testbench_isim_beh.exe.sim/
verilog/lab1/Flow_lab/isim/testbench_isim_beh.exe.sim/isimcrash.log
verilog/lab1/Flow_lab/isim/testbench_isim_beh.exe.sim/ISimEngine-DesignHierarchy.dbg
verilog/lab1/Flow_lab/isim/testbench_isim_beh.exe.sim/isimkernel.log
verilog/lab1/Flow_lab/isim/testbench_isim_beh.exe.sim/netId.dat
verilog/lab1/Flow_lab/isim/testbench_isim_beh.exe.sim/testbench_isim_beh.exe
verilog/lab1/Flow_lab/isim/testbench_isim_beh.exe.sim/tmp_save/
verilog/lab1/Flow_lab/isim/testbench_isim_beh.exe.sim/tmp_save/_1
verilog/lab1/Flow_lab/isim/testbench_isim_beh.exe.sim/unisims_ver/
verilog/lab1/Flow_lab/isim/testbench_isim_beh.exe.sim/unisims_ver/m_00000000000053605399_0773046326.c
verilog/lab1/Flow_lab/isim/testbench_isim_beh.exe.sim/unisims_ver/m_00000000000053605399_0773046326.didat
verilog/lab1/Flow_lab/isim/testbench_isim_beh.exe.sim/unisims_ver/m_00000000000053605399_0773046326.nt.obj
verilog/lab1/Flow_lab/isim/testbench_isim_beh.exe.sim/unisims_ver/m_00000000000129024098_1730278898.c
verilog/lab1/Flow_lab/isim/testbench_isim_beh.exe.sim/unisims_ver/m_00000000000129024098_1730278898.didat
verilog/lab1/Flow_lab/isim/testbench_isim_beh.exe.sim/unisims_ver/m_00000000000129024098_1730278898.nt.obj
verilog/lab1/Flow_lab/isim/testbench_isim_beh.exe.sim/unisims_ver/m_00000000000236260522_2449448540.c
verilog/lab1/Flow_lab/isim/testbench_isim_beh.exe.sim/unisims_ver/m_00000000000236260522_2449448540.didat
verilog/lab1/Flow_lab/isim/testbench_isim_beh.exe.sim/unisims_ver/m_00000000000236260522_2449448540.nt.obj
verilog/lab1/Flow_lab/isim/testbench_isim_beh.exe.sim/unisims_ver/m_00000000000909115699_2771340377.c
verilog/lab1/Flow_lab/isim/testbench_isim_beh.exe.sim/unisims_ver/m_00000000000909115699_2771340377.didat
verilog/lab1/Flow_lab/isim/testbench_isim_beh.exe.sim/unisims_ver/m_00000000000909115699_2771340377.nt.obj
verilog/lab1/Flow_lab/isim/testbench_isim_beh.exe.sim/unisims_ver/m_00000000000950279619_0270976356.c
verilog/lab1/Flow_lab/isim/testbench_isim_beh.exe.sim/unisims_ver/m_00000000000950279619_0270976356.didat
verilog/lab1/Flow_lab/isim/testbench_isim_beh.exe.sim/unisims_ver/m_00000000000950279619_0270976356.nt.obj
verilog/lab1/Flow_lab/isim/testbench_isim_beh.exe.sim/unisims_ver/m_00000000001108370118_0424564230.didat
verilog/lab1/Flow_lab/isim/testbench_isim_beh.exe.sim/unisims_ver/m_00000000001108370118_0426657133.didat
verilog/lab1/Flow_lab/isim/testbench_isim_beh.exe.sim/unisims_ver/m_00000000001108370118_0861236213.didat
verilog/lab1/Flow_lab/isim/testbench_isim_beh.exe.sim/unisims_ver/m_00000000001108370118_1483506755.didat
verilog/lab1/Flow_lab/isim/testbench_isim_beh.exe.sim/unisims_ver/m_00000000001108370118_1692160999.c
verilog/lab1/Flow_lab/isim/testbench_isim_beh.exe.sim/unisims_ver/m_00000000001108370118_1692160999.didat
verilog/lab1/Flow_lab/isim/testbench_isim_beh.exe.sim/unisims_ver/m_00000000001108370118_1692160999.nt.obj
verilog/lab1/Flow_lab/isim/testbench_isim_beh.exe.sim/unisims_ver/m_00000000001108370118_1954070447.didat
verilog/lab1/Flow_lab/isim/testbench_isim_beh.exe.sim/unisims_ver/m_00000000001108370118_2467748173.didat
verilog/lab1/Flow_lab/isim/testbench_isim_beh.exe.sim/unisims_ver/m_00000000001108370118_3299605463.didat
verilog/lab1/Flow_lab/isim/testbench_isim_beh.exe.sim/unisims_ver/m_00000000001108370118_3526530760.didat
verilog/lab1/Flow_lab/isim/testbench_isim_beh.exe.sim/unisims_ver/m_00000000001361930395_1453400397.c
verilog/lab1/Flow_lab/isim/testbench_isim_beh.exe.sim/unisims_ver/m_00000000001361930395_1453400397.didat
verilog/lab1/Flow_lab/isim/testbench_isim_beh.exe.sim/unisims_ver/m_00000000001361930395_1453400397.nt.obj
verilog/lab1/Flow_lab/isim/testbench_isim_beh.exe.sim/unisims_ver/m_00000000001508379050_3852734344.c
verilog/lab1/Flow_lab/isim/testbench_isim_beh.exe.sim/unisims_ver/m_00000000001508379050_3852734344.didat
verilog/lab1/Flow_lab/isim/testbench_isim_beh.exe.sim/unisims_ver/m_00000000001508379050_3852734344.nt.obj
verilog/lab1/Flow_lab/isim/testbench_isim_beh.exe.sim/unisims_ver/m_00000000001773747898_0257217429.didat
verilog/lab1/Flow_lab/isim/testbench_isim_beh.exe.sim/unisims_ver/m_00000000001773747898_2935195057.c
verilog/lab1/Flow_lab/isim/testbench_isim_beh.exe.sim/unisims_ver/m_00000000001773747898_2935195057.didat
verilog/lab1/Flow_lab/isim/testbench_isim_beh.exe.sim/unisims_ver/m_00000000001773747898_2935195057.nt.obj
verilog/lab1/Flow_lab/isim/testbench_isim_beh.exe.sim/unisims_ver/m_00000000001773747898_3085481200.didat
verilog/lab1/Flow_lab/isim/testbench

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