文件名称:Vfirr_using__e
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- 上传时间:2012-11-16
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文件大小:23.95kb
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一种基于verilog的fiir滤波,并带matlab仿真
-Based verilog fiir filter with matlab simulation
-Based verilog fiir filter with matlab simulation
(系统自动生成,下载前可以参看下载内容)
下载文件列表
Vfirr_using__e/fir_using_FPGA/adder.v
Vfirr_using__e/fir_using_FPGA/basic_fir.m
Vfirr_using__e/fir_using_FPGA/Basic_FIR.v
Vfirr_using__e/fir_using_FPGA/coeff_0_7.mif
Vfirr_using__e/fir_using_FPGA/coeff_1_6.mif
Vfirr_using__e/fir_using_FPGA/coeff_2_5.mif
Vfirr_using__e/fir_using_FPGA/coeff_3_4.mif
Vfirr_using__e/fir_using_FPGA/coeff_rom_0_7.v
Vfirr_using__e/fir_using_FPGA/coeff_rom_1_6.v
Vfirr_using__e/fir_using_FPGA/coeff_rom_2_5.v
Vfirr_using__e/fir_using_FPGA/coeff_rom_3_4.v
Vfirr_using__e/fir_using_FPGA/db/fir.db_info
Vfirr_using__e/fir_using_FPGA/db/fir.eco.cdb
Vfirr_using__e/fir_using_FPGA/db/fir.sld_design_entry.sci
Vfirr_using__e/fir_using_FPGA/fir.qpf
Vfirr_using__e/fir_using_FPGA/fir.qsf
Vfirr_using__e/fir_using_FPGA/fir.qws
Vfirr_using__e/fir_using_FPGA/impulse.vwf
Vfirr_using__e/fir_using_FPGA/mult_add.v
Vfirr_using__e/fir_using_FPGA/random.vwf
Vfirr_using__e/fir_using_FPGA/step.vwf
Vfirr_using__e/fir_using_FPGA/db
Vfirr_using__e/fir_using_FPGA
Vfirr_using__e
Vfirr_using__e/fir_using_FPGA/basic_fir.m
Vfirr_using__e/fir_using_FPGA/Basic_FIR.v
Vfirr_using__e/fir_using_FPGA/coeff_0_7.mif
Vfirr_using__e/fir_using_FPGA/coeff_1_6.mif
Vfirr_using__e/fir_using_FPGA/coeff_2_5.mif
Vfirr_using__e/fir_using_FPGA/coeff_3_4.mif
Vfirr_using__e/fir_using_FPGA/coeff_rom_0_7.v
Vfirr_using__e/fir_using_FPGA/coeff_rom_1_6.v
Vfirr_using__e/fir_using_FPGA/coeff_rom_2_5.v
Vfirr_using__e/fir_using_FPGA/coeff_rom_3_4.v
Vfirr_using__e/fir_using_FPGA/db/fir.db_info
Vfirr_using__e/fir_using_FPGA/db/fir.eco.cdb
Vfirr_using__e/fir_using_FPGA/db/fir.sld_design_entry.sci
Vfirr_using__e/fir_using_FPGA/fir.qpf
Vfirr_using__e/fir_using_FPGA/fir.qsf
Vfirr_using__e/fir_using_FPGA/fir.qws
Vfirr_using__e/fir_using_FPGA/impulse.vwf
Vfirr_using__e/fir_using_FPGA/mult_add.v
Vfirr_using__e/fir_using_FPGA/random.vwf
Vfirr_using__e/fir_using_FPGA/step.vwf
Vfirr_using__e/fir_using_FPGA/db
Vfirr_using__e/fir_using_FPGA
Vfirr_using__e
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