文件名称:sim
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- 上传时间：2012-11-16
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文件大小：15.84mb
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时钟倍频后，通过Modelsim仿真验证任意占空比可调的PWM信号-After the clock multiplier, through Modelsim simulation arbitrary variable duty cycle PWM signal
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下载文件列表
sim/glbl.v
sim/pwm_div.cr.mti
sim/pwm_div.mpf
sim/pwm_div.v
sim/pwm_div.v.bak
sim/rom16.mif
sim/rom16.v
sim/tb.v
sim/transcript
sim/vsim.wlf
sim/wave.do
sim/work/@p@w@m_div/verilog.asm
sim/work/@p@w@m_div/verilog.rw
sim/work/@p@w@m_div/_primary.dat
sim/work/@p@w@m_div/_primary.dbs
sim/work/@p@w@m_div/_primary.vhd
sim/work/glbl/verilog.asm
sim/work/glbl/verilog.rw
sim/work/glbl/_primary.dat
sim/work/glbl/_primary.dbs
sim/work/glbl/_primary.vhd
sim/work/rom16/verilog.asm
sim/work/rom16/verilog.rw
sim/work/rom16/_primary.dat
sim/work/rom16/_primary.dbs
sim/work/rom16/_primary.vhd
sim/work/tb/verilog.asm
sim/work/tb/verilog.rw
sim/work/tb/_primary.dat
sim/work/tb/_primary.dbs
sim/work/tb/_primary.vhd
sim/work/_info
sim/work/_vmake
sim/work/@p@w@m_div
sim/work/glbl
sim/work/rom16
sim/work/tb
sim/work/_temp
sim/work
sim
sim/pwm_div.cr.mti
sim/pwm_div.mpf
sim/pwm_div.v
sim/pwm_div.v.bak
sim/rom16.mif
sim/rom16.v
sim/tb.v
sim/transcript
sim/vsim.wlf
sim/wave.do
sim/work/@p@w@m_div/verilog.asm
sim/work/@p@w@m_div/verilog.rw
sim/work/@p@w@m_div/_primary.dat
sim/work/@p@w@m_div/_primary.dbs
sim/work/@p@w@m_div/_primary.vhd
sim/work/glbl/verilog.asm
sim/work/glbl/verilog.rw
sim/work/glbl/_primary.dat
sim/work/glbl/_primary.dbs
sim/work/glbl/_primary.vhd
sim/work/rom16/verilog.asm
sim/work/rom16/verilog.rw
sim/work/rom16/_primary.dat
sim/work/rom16/_primary.dbs
sim/work/rom16/_primary.vhd
sim/work/tb/verilog.asm
sim/work/tb/verilog.rw
sim/work/tb/_primary.dat
sim/work/tb/_primary.dbs
sim/work/tb/_primary.vhd
sim/work/_info
sim/work/_vmake
sim/work/@p@w@m_div
sim/work/glbl
sim/work/rom16
sim/work/tb
sim/work/_temp
sim/work
sim
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