资源列表
chengfa
- 用VerilogHDL的16*16乘法器的设计实现，采用的是移位相乘方法-VerilogHDL with 16* 16 multiplier design using the method of displacement multiplied
basic_aco
- basic ant algrithmic
pwm
- PWM 3色全彩LED控制，使用7219辅助调试，手动变色，每色7档。-PWM 3-color full-color LED control, the use of 7219 secondary debugging, manual color, each color 7 files.
shortestroad
- 这是大学中计算机专业学生的作业，最短路径，如果不会做，可以下载参考-This is a university student in computer specialty operations, shortest path, if not, can download information
svm_gui
- 界面化的SVM更方便于编程计算着计算，分析。对于编程比较薄弱的人员比较方便。-Interface of the program makes it easier to calculate SVM with calculation and analysis. For relatively weak programming staff more convenient.
AVO_FINAL2
- AVO ANALYSIS NEEDS COEFFICIENTS REFLECTIVITY
mrxxkscq
- 生成一个骂人的信息框，支持图标，有“错误图标”“警告图标”“信息图标”等~-look you mother fly in the sky！
cadence-16.2-introduce
- cadence 16.2各应用程序和架构简介-cadence 16.2 Introduction to the application and architecture
ADLL-verilog-code
- 数字锁相环的设计代码，完整的，希望能帮到大家-PLL phase-locked loop
463772cppsource
- 用汇编语言编写一个时钟程序，在微机屏幕上显示当前时间的时，分，秒。在程序启动后，可键入当前时间，回车键按下后，开始计时-Using assembly language to write a clock procedures, display the current time, divided on the PC screen, seconds. After the program started, can enter the current time, the Enter key is pres
123
- 我了个屈！这是个很牛掰的程序。不看这辈子后悔，下辈子网布了。-I had a pike! This is a very cattle breaking procedure. Do not look to regret this life, next life mesh cloth.
p12-6060-Akhwand-Abdul-kareem-Database-Lab-Final-
- it is a useless file do not open it or dowload it