verilog实例/ADC_16bit.v
verilog实例/adder_8bit.v
verilog实例/adder_8bit_2.v
verilog实例/ALL.V
verilog实例/binarytogray.v
verilog实例/cla_8bits.v
verilog实例/COMPARE.V
verilog实例/dds.v
verilog实例/DECODER1.V
verilog实例/decoder3x8.v
verilog实例/div16.v
verilog实例/encoder8x3.v
verilog实例/encoder8x3_2.v
verilog实例/fifo.v
verilog实例/fifo_16x16.v
verilog实例/FIFO_2.V
verilog实例/framer.v
verilog实例/frequency5x2.v
verilog实例/full_adder_1.v
verilog实例/full_adder_2.v
verilog实例/gencrc.v.txt
verilog实例/half_adder_1.v
verilog实例/half_adder_2.v
verilog实例/half_adder_3.v
verilog实例/lead_8bits_adder.v
verilog实例/lead_8bits_adder2.v
verilog实例/MUL16.V
verilog实例/mult16.v
verilog实例/multi_select_1.v
verilog实例/mult_piped_8x8.v
verilog实例/mult_select.v
verilog实例/MUX8X8.V
verilog实例/myrand.c
verilog实例/nco.v
verilog实例/onehot.v
verilog实例/pic.v
verilog实例/PLI.TAR
verilog实例/RISC8.ZIP
verilog实例/sequence_dectect.v
verilog实例/SHIFTER.V
verilog实例/string.v
verilog实例/SYNTHPIC.ZIP
verilog实例/TEST.V
verilog实例/testing.v.txt
verilog实例/test_cla_8bits.v
verilog实例/wpulse.v.txt
verilog实例