CDN加速镜像 | 设为首页 | 加入收藏夹
当前位置: 首页 文档资料 行业发展研究

资源列表

« 1 2 ... .12 .13 .14 .15 .16 717.18 .19 .20 .21 .22 ... 1013 »
  1. Backtracking

    0下载:
  2. Bactracking algorithm course
  3. 所属分类:Development Research

    • 发布日期:2017-05-03
    • 文件大小:810.14kb
    • 提供者:2k
  1. Dynamic_Programmation

    0下载:
  2. Dynamic Programmation Course
  3. 所属分类:Development Research

    • 发布日期:2017-05-03
    • 文件大小:615.7kb
    • 提供者:2k
  1. Heuristics

    0下载:
  2. Heuristics algorithm course
  3. 所属分类:Development Research

    • 发布日期:2017-05-03
    • 文件大小:610.25kb
    • 提供者:2k
  1. NP_COmpetude

    0下载:
  2. NP completude course
  3. 所属分类:Development Research

    • 发布日期:2017-04-26
    • 文件大小:443.48kb
    • 提供者:2k
  1. IOS236_Installer_v6

    0下载:
  2. ios236 installer for nintendo wii software.
  3. 所属分类:Development Research

    • 发布日期:2017-05-03
    • 文件大小:519.42kb
    • 提供者:brod
  1. d2x-cIOS-Installer-v3.1

    1下载:
  2. cios installer for wii homebrew channel
  3. 所属分类:Development Research

    • 发布日期:2017-03-27
    • 文件大小:546.54kb
    • 提供者:brod
  1. LowPowerTechniques

    0下载:
  2. Low Power Design Nano‐scale designs at 130nm and below are now confronted with a power dissipation level beyond the limits of IC packaging and cooling techniques • Consequently in many designs it is not possible to increase the clock speed
  3. 所属分类:Development Research

    • 发布日期:2017-05-02
    • 文件大小:632.2kb
    • 提供者:yosso
  1. physicalDesign

    0下载:
  2. IL2200ASIC Design  Physical Implementation Styles  ASIC Design Flow  Floor and Power planning  Placement  Clock Tree Synthesis  Routing  Timing Analysis  Verification and Ener
  3. 所属分类:Development Research

    • 发布日期:2017-05-09
    • 文件大小:1.57mb
    • 提供者:yosso
  1. PLC-note

    0下载:
  2. PLC note Design and Implementation of A DSSSBased Narrow Band Power Line Communication Modem
  3. 所属分类:Development Research

    • 发布日期:2017-05-13
    • 文件大小:2.67mb
    • 提供者:yosso
  1. RTL-coding-guidelines

    0下载:
  2. RTL coding guidelines Offer a collection of coding rules and guidelines. Make HDL Codes readable, modifiable, and reusable. Achieve optimal results in synthesis and simulation.
  3. 所属分类:Development Research

    • 发布日期:2017-04-27
    • 文件大小:406.96kb
    • 提供者:yosso
  1. tutorial_asic_v12_1

    0下载:
  2. tutorial_asic_v12_1 Digital Design Flow Tutorial for EDA Tools: Synopsys Design Compiler Mentor Modelsim Cadence SOC Encounter
  3. 所属分类:Development Research

    • 发布日期:2017-05-09
    • 文件大小:1.53mb
    • 提供者:yosso
  1. verilog_intro-Cygwin

    0下载:
  2. verilog_intro-Cygwin environment and as a design tool. The Cadence design tool suite is installed on the Linux servers on our network. We will use be using the GUI interface which will allow us to view waveforms in a timing diagram. This also r
  3. 所属分类:Development Research

    • 发布日期:2017-05-03
    • 文件大小:552.2kb
    • 提供者:yosso
« 1 2 ... .12 .13 .14 .15 .16 717.18 .19 .20 .21 .22 ... 1013 »
搜珍网 www.dssz.com