资源列表
BBR-for-SALBP1
- BRANCH AND BOUND ASSEMBLY LINE DATA
S1
- SET OF PROGRAMS FOR ASSEMBLY LINE BLOCKING PARAMETERS
Salt-sensing-inversion-
- 遥感盐分反演,介绍了matlab进行数学建模,并采用bp神经网络等内容-Remote sensing of salt inversion, introduced matlab mathematical modeling, and the use of neural networks and other content bp
74HC_HCT245
- Datasheet for HCT245 integrated circuit.
74HC_HCT259
- Datasheet for HCT259 integrated circuit.
74HC573
- Datasheet for HC573 integrated circuit.
74HC574
- Datasheet for HC574 integrated circuit.
74HC595
- Datasheet for HC595 integrated circuit.
An-algorithm-for-linear-constrained-adaptive-arra
- An algorithm for linear constrained adaptive array processing
a-design-of-8b_10bSerDes
- 。论文首先给出了8b/10bSerDes的系 统结构,将其分为发送端和接收端两个部分,然后按照功能的不同,对电路进 行了模块划分,并且设计了其中的4个主要模块.8b/10b编码模块、8b/10b解码 模块、10:1并串转换模块和1:10串并转换模块。-A Design of 8b/1 0bSerDes
HIGH-8B_10B-DECODE-ASIC
- 本文重点研究了高速8b/10b解码器的设计与实现,在详细介绍了解码原理及 多种传统解码方案的基础上,采用流水线结构设计了高速8b/10b解码器。通过 仔细分析传统解码器的不足,精心设计流水线结构及触发器在关键路径上的插入 点,使得所设计电路的速度比传统解码器有了较大的提升。-This paper focuses on the 8b/l 0b decoder,including the decoding principles and a variety of decoding sc
SerDes
- 12.5 Gb/s半速率时钟数据恢复电路(CDR)的 设计及6.25Gb/s SerDes接收芯片的系统集成,设计工艺均为TSMC 0.189in CMOS工艺。-aspects:Design of Half-rate 1 2.5 Gb/s Clock Data Recovery (CDR)and Integration of 6.25Gb/s SerDes receiver.Both are realized in TSMC 0.1 89m CMOS process.