资源列表
doctordegree3
- 运动目标分割的博士论文 西安电子大学 李玉山博导-moving target segmentation doctoral dissertation, Xi'an University of Electronic Li Yushan doctoral
papersaboutSYNTHESIS3dface
- 这是几篇对做特定三维人脸建模的朋友比较有参考意义的论文资料，方法都比较有代表性！-This is so specific a few pairs of 3-D Face Modeling friends compared to the reference paper, methods more representative!
EasywayforGIS
- 打破GIS体系中存在的某些垄断。让掌握地理数据的的第一线人员可以自行建造相关地图。-GIS system to break the monopoly of certain. Let master of geographic data on the first line of officers to the construction of associated maps.
fmccluster
- FCM聚类算法介绍-FCM clustering algorithm introduced
AlusterAnalysis
- 聚类分析算法.pdf-cluster analysis algorithm. Pdf
CameraAnalysis
- 奥林巴斯4/3系统单反E-1专业数码相机分析. -Olympus 4 / 3 system Simple E-1 professional digital camera analysis.
socEmergingTechnologies
- SOC设计是国内目前的热点方向。原因是SOC可以降低设备成本，降低功耗，提高集成度、面积、可靠性…这为提高自主知识产权和降低对国外芯片的依赖性有着重大的意义。我们看到，国内的SOC设计水平也在逐步提高。-SOC design is the current hot direction. The reason is SOC can reduce equipment costs, reduce power consumption and enhance integration, size and re
IC_design_industry[1]
- 随着集成电路产业的超快速发展,IC设计业已成为主流趋势,每日更新EDA设计及IC设计的新闻趋势和新产品动态,提供IC设计技术文库和应用实例.介绍EDA工具的使用,帮助工程师们更深入理解EDA设计及IC设计技术,并实践到工作中。 -With the integrated circuit industry ultra-rapid development of IC design has become a mainstream trend. EDA updated daily IC d
Pipeline_synchronization
- Pipeline synchronization is a simple, low-cost, highbandwidth,highreliability solution to interfaces between synchronous and asynchronous systems, or between synchronous systems operating from different clocks.-Pipeline synchronization is a simple,
soc_developments_in_eight_years
- 20世纪90年代中期，因使用ASIC实现芯片组受到启发，萌生应该将完整计算机所有不同的功能块一 次直接集成于一颗硅片上的想法。这种芯片，初始起名叫System on a Chip(SoC)，直译的中文名是 系统级芯片-20th century and mid-1990s, the use of ASIC chip group be inspired by this, initiation should be complete computer all the different func
System_on_Chip_Reuse
- Pre-designed and pre-verified hardware and software blocks can be combined on chips for many different applicationsVthey promise large productivity gains.-Pre-designed and pre-verified hardware a nd software blocks can be combined on chips for m an
interfaces_for_mixed_timing_systems
- This paper presents several low-latency mixed-timing FIFO (first-in–first-out) interfaces designs that interface systems on a chip working at different speeds. The connected systems can be either synchronous or asynchronous. The designs are the