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文件名称:USB_project

  • 所属分类：
    USB develop
  • 标签属性：
    [HTML]
  • 上传时间：
    2012-11-16
  • 文件大小：
    6.73mb
  • 已下载：
    0次
  • 提 供 者：
    Ngo****
  • 相关连接：
    无
  • 下载说明：
    别用迅雷下载，失败请重下，重下不扣分！
修正介绍说明

介绍说明－－下载内容来自于网络，使用问题请自行百度

USB interface FPGA

USB: CY680013CA

FPGA: Xilinx, Altera


(系统自动生成,下载前可以参看下载内容)

下载文件列表

EU_project/blockdiagram/.dswkshop/MdtSvgBLKD_Dimensions.xsl
EU_project/blockdiagram/.dswkshop/MdtSvgDiag_Colors.xsl
EU_project/blockdiagram/.dswkshop/MdtSvgDiag_Globals.xsl
EU_project/blockdiagram/.dswkshop/MdtSvgDiag_StyleDefs.css
EU_project/blockdiagram/.dswkshop/MdtTinySvgBLKD_BusLaneSpaces.xsl
EU_project/blockdiagram/.dswkshop/MdtTinySvgBLKD_Busses.xsl
EU_project/blockdiagram/.dswkshop/MdtTinySvgBLKD_Functions.xsl
EU_project/blockdiagram/.dswkshop/MdtTinySvgBLKD_Globals.xsl
EU_project/blockdiagram/.dswkshop/MdtTinySvgBLKD_IOPorts.xsl
EU_project/blockdiagram/.dswkshop/MdtTinySvgBLKD_Main.xsl
EU_project/blockdiagram/.dswkshop/MdtTinySvgBLKD_Peripherals.xsl
EU_project/blockdiagram/.dswkshop/MdtTinySvgBLKD_Processors.xsl
EU_project/blockdiagram/.dswkshop/MdtTinySvgBLKD_StyleDefs.xsl
EU_project/blockdiagram/.dswkshop/MdtTinySvgDiag_BifShapes.xsl
EU_project/blockdiagram/.dswkshop/MdtXdsGen_Colors.xsl
EU_project/blockdiagram/.dswkshop/MdtXdsGen_Globals.xsl
EU_project/blockdiagram/.dswkshop/MdtXdsGen_HTMLDatasheet.css
EU_project/blockdiagram/.dswkshop/MdtXdsGen_HTMLDatasheet.xsl
EU_project/blockdiagram/.dswkshop/MdtXdsGen_HTMLIPSection.xsl
EU_project/blockdiagram/.dswkshop/MdtXdsGen_HTMLMemoryMap.xsl
EU_project/blockdiagram/.dswkshop/MdtXdsGen_HTMLTOCTree.xsl
EU_project/blockdiagram/.dswkshop/svg10.dtd
EU_project/blockdiagram/.dswkshop/system_w_blkd.xml
EU_project/blockdiagram/svg10.dtd
EU_project/blockdiagram/system.css
EU_project/blockdiagram/system.svg
EU_project/clock_generator_0.log
EU_project/data/system.ucf
EU_project/etc/bitgen.ut
EU_project/etc/download.cmd
EU_project/etc/fast_runtime.opt
EU_project/pcores/cyusb_v1_00_a/data/cyusb_v2_1_0.mpd
EU_project/pcores/cyusb_v1_00_a/data/cyusb_v2_1_0.pao
EU_project/pcores/cyusb_v1_00_a/devl/ipwiz.log
EU_project/pcores/cyusb_v1_00_a/hdl/vhdl/cyusb.vhd
EU_project/pcores/cyusb_v1_00_a/hdl/vhdl/rom_tx.vhd
EU_project/pcores/cyusb_v1_00_a/hdl/vhdl/rx_frame.vhd
EU_project/pcores/cyusb_v1_00_a/hdl/vhdl/trancever_modul.vhd
EU_project/pcores/cyusb_v1_00_a/hdl/vhdl/tx_frame.vhd
EU_project/pcores/cyusb_v1_00_a/hdl/vhdl/usb_controller.vhd
EU_project/pcores/cy_controller_v1_00_a/data/cy_controller_v2_1_0.mpd
EU_project/pcores/cy_controller_v1_00_a/data/cy_controller_v2_1_0.pao
EU_project/pcores/cy_controller_v1_00_a/data/_cy_controller_xst.prj
EU_project/pcores/cy_controller_v1_00_a/data_old/cy_controller_v2_1_0.mpd
EU_project/pcores/cy_controller_v1_00_a/data_old/cy_controller_v2_1_0.pao
EU_project/pcores/cy_controller_v1_00_a/devl/create.cip
EU_project/pcores/cy_controller_v1_00_a/devl/ipwiz.log
EU_project/pcores/cy_controller_v1_00_a/devl/ipwiz.opt
EU_project/pcores/cy_controller_v1_00_a/devl/projnav/.lso
EU_project/pcores/cy_controller_v1_00_a/devl/projnav/cy_controller.gise
EU_project/pcores/cy_controller_v1_00_a/devl/projnav/cy_controller.ise
EU_project/pcores/cy_controller_v1_00_a/devl/projnav/cy_controller.prj
EU_project/pcores/cy_controller_v1_00_a/devl/projnav/cy_controller.stx
EU_project/pcores/cy_controller_v1_00_a/devl/projnav/cy_controller.tcl
EU_project/pcores/cy_controller_v1_00_a/devl/projnav/cy_controller.xise
EU_project/pcores/cy_controller_v1_00_a/devl/projnav/cy_controller.xst
EU_project/pcores/cy_controller_v1_00_a/devl/projnav/cy_controller_summary.html
EU_project/pcores/cy_controller_v1_00_a/devl/projnav/cy_controller_vhdl.prj
EU_project/pcores/cy_controller_v1_00_a/devl/projnav/cy_controller_xdb/tmp/ise/version
EU_project/pcores/cy_controller_v1_00_a/devl/projnav/cy_controller_xdb/tmp/ise/__OBJSTORE__/HierarchicalDesign/HDProject/HDProject
EU_project/pcores/cy_controller_v1_00_a/devl/projnav/cy_controller_xdb/tmp/ise/__OBJSTORE__/HierarchicalDesign/HDProject/HDProject_StrTbl
EU_project/pcores/cy_controller_v1_00_a/devl/projnav/cy_controller_xdb/tmp/ise/__OBJSTORE__/HierarchicalDesign/__stored_object_table__
EU_project/pcores/cy_controller_v1_00_a/devl/projnav/cy_controller_xdb/tmp/ise/__OBJSTORE__/PnAutoRun/Scripts/RunOnce_tcl
EU_project/pcores/cy_controller_v1_00_a/devl/projnav/cy_controller_xdb/tmp/ise/__OBJSTORE__/PnAutoRun/Scripts/RunOnce_tcl_StrTbl
EU_project/pcores/cy_controller_v1_00_a/devl/projnav/cy_controller_xdb/tmp/ise/__OBJSTORE__/ProjectNavigator/dpm_project_main/dpm_project_main
EU_project/pcores/cy_controller_v1_00_a/devl/projnav/cy_controller_xdb/tmp/ise/__OBJSTORE__/ProjectNavigator/dpm_project_main/dpm_project_main_StrTbl
EU_project/pcores/cy_controller_v1_00_a/devl/projnav/cy_controller_xdb/tmp/ise/__OBJSTORE__/ProjectNavigatorGui/CViewSelector
EU_project/pcores/cy_controller_v1_00_a/devl/projnav/cy_controller_xdb/tmp/ise/__OBJSTORE__/ProjectNavigatorGui/CViewSelector_StrTbl
EU_project/pcores/cy_controller_v1_00_a/devl/projnav/cy_controller_xdb/tmp/ise/__OBJSTORE__/ProjectNavigatorGui/File-SynthesisOnly
EU_project/pcores/cy_controller_v1_00_a/devl/projnav/cy_controller_xdb/tmp/ise/__OBJSTORE__/ProjectNavigatorGui/File-SynthesisOnly_StrTbl
EU_project/pcores/cy_controller_v1_00_a/devl/projnav/cy_controller_xdb/tmp/ise/__OBJSTORE__/ProjectNavigatorGui/Library-SynthesisOnly
EU_project/pcores/cy_controller_v1_00_a/devl/projnav/cy_controller_xdb/tmp/ise/_

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