文件名称:DE2_NET
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- 上传时间:2012-11-16
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文件大小:1.53mb
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已下载:0次
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DE2 System on chip design. The design is for testing peripheral being available in system
(系统自动生成,下载前可以参看下载内容)
下载文件列表
DE2_NET/.metadata/.lock
DE2_NET/.metadata/.plugins/org.eclipse.core.resources/.projects/hello_led_0/.properties
DE2_NET/.metadata/.plugins/org.eclipse.core.resources/.projects/hello_led_0_syslib/.properties
DE2_NET/.metadata/.plugins/org.eclipse.core.resources/.root/9.tree
DE2_NET/.metadata/.plugins/org.eclipse.core.resources/.safetable/org.eclipse.core.resources
DE2_NET/.metadata/.plugins/org.eclipse.core.runtime/.settings/org.eclipse.cdt.core.prefs
DE2_NET/.metadata/.plugins/org.eclipse.core.runtime/.settings/org.eclipse.cdt.debug.core.prefs
DE2_NET/.metadata/.plugins/org.eclipse.core.runtime/.settings/org.eclipse.cdt.ui.prefs
DE2_NET/.metadata/.plugins/org.eclipse.core.runtime/.settings/org.eclipse.team.cvs.ui.prefs
DE2_NET/.metadata/.plugins/org.eclipse.core.runtime/.settings/org.eclipse.team.ui.prefs
DE2_NET/.metadata/.plugins/org.eclipse.core.runtime/.settings/org.eclipse.ui.prefs
DE2_NET/.metadata/.plugins/org.eclipse.core.runtime/.settings/org.eclipse.ui.workbench.prefs
DE2_NET/.metadata/.plugins/org.eclipse.ui.workbench/dialog_settings.xml
DE2_NET/.metadata/.plugins/org.eclipse.ui.workbench/workbench.xml
DE2_NET/.metadata/version.ini
DE2_NET/.sopc_builder/install.ptf
DE2_NET/altpllpll_0.ppf
DE2_NET/Audio_0.v
DE2_NET/Audio_DAC_FIFO/cb_generator.pl
DE2_NET/Audio_DAC_FIFO/class.ptf
DE2_NET/Audio_DAC_FIFO/hdl/AUDIO_DAC_FIFO.v
DE2_NET/Audio_DAC_FIFO/hdl/FIFO_16_256.v
DE2_NET/AUDIO_DAC_FIFO.v
DE2_NET/Audio_PLL.ppf
DE2_NET/Audio_PLL.v
DE2_NET/bht_ram.mif
DE2_NET/Binary_VGA_Controller/cb_generator.pl
DE2_NET/Binary_VGA_Controller/class.ptf
DE2_NET/Binary_VGA_Controller/hdl/Img_DATA.hex
DE2_NET/Binary_VGA_Controller/hdl/Img_RAM.v
DE2_NET/Binary_VGA_Controller/hdl/VGA_Controller.v
DE2_NET/Binary_VGA_Controller/hdl/VGA_NIOS_CTRL.v
DE2_NET/Binary_VGA_Controller/hdl/VGA_OSD_RAM.v
DE2_NET/Binary_VGA_Controller/hdl/VGA_Param.h
DE2_NET/Binary_VGA_Controller/inc/VGA.c
DE2_NET/Binary_VGA_Controller/inc/VGA.h
DE2_NET/button_pio.v
DE2_NET/clock_0.v
DE2_NET/clock_1.v
DE2_NET/cpu_0.ocp
DE2_NET/cpu_0.v
DE2_NET/cpu_0.vo
DE2_NET/cpu_0_bht_ram.mif
DE2_NET/cpu_0_dc_tag_ram.mif
DE2_NET/cpu_0_ic_tag_ram.mif
DE2_NET/cpu_0_jtag_debug_module.v
DE2_NET/cpu_0_jtag_debug_module_wrapper.v
DE2_NET/cpu_0_mult_cell.v
DE2_NET/cpu_0_ociram_default_contents.mif
DE2_NET/cpu_0_rf_ram_a.mif
DE2_NET/cpu_0_rf_ram_b.mif
DE2_NET/cpu_0_test_bench.v
DE2_NET/dc_tag_ram.mif
DE2_NET/DE2_Board/class.ptf
DE2_NET/DE2_Board/system/.sopc_builder/install.ptf
DE2_NET/DE2_Board/system/asmi.v
DE2_NET/DE2_Board/system/cmp_state.ini
DE2_NET/DE2_Board/system/cpu_0.ocp
DE2_NET/DE2_Board/system/cpu_0.v
DE2_NET/DE2_Board/system/cpu_0_test_bench.v
DE2_NET/DE2_Board/system/data_RAM.hex
DE2_NET/DE2_Board/system/data_RAM.v
DE2_NET/DE2_Board/system/DE2_Board.asm.rpt
DE2_NET/DE2_Board/system/DE2_Board.bsf
DE2_NET/DE2_Board/system/DE2_Board.cdf
DE2_NET/DE2_Board/system/DE2_Board.done
DE2_NET/DE2_Board/system/DE2_Board.fit.eqn
DE2_NET/DE2_Board/system/DE2_Board.fit.rpt
DE2_NET/DE2_Board/system/DE2_Board.fit.summary
DE2_NET/DE2_Board/system/DE2_Board.flow.rpt
DE2_NET/DE2_Board/system/DE2_Board.map.eqn
DE2_NET/DE2_Board/system/DE2_Board.map.rpt
DE2_NET/DE2_Board/system/DE2_Board.map.summary
DE2_NET/DE2_Board/system/DE2_Board.pin
DE2_NET/DE2_Board/system/DE2_Board.pof
DE2_NET/DE2_Board/system/DE2_Board.ptf
DE2_NET/DE2_Board/system/DE2_Board.ptf.5.00
DE2_NET/DE2_Board/system/DE2_Board.ptf.bak
DE2_NET/DE2_Board/system/DE2_Board.qpf
DE2_NET/DE2_Board/system/DE2_Board.qsf
DE2_NET/DE2_Board/system/DE2_Board.qws
DE2_NET/DE2_Board/system/DE2_Board.sof
DE2_NET/DE2_Board/system/DE2_Board.tan.rpt
DE2_NET/DE2_Board/system/DE2_Board.tan.summary
DE2_NET/DE2_Board/system/DE2_Board.v
DE2_NET/DE2_Board/system/DE2_Board_assignment_defaults.qdf
DE2_NET/DE2_Board/system/DE2_Board_generation_script
DE2_NET/DE2_Board/system/DE2_Board_log.txt
DE2_NET/DE2_Board/system/DE2_Board_setup_quartus.tcl
DE2_NET/DE2_Board/system/DE2_Board_sim/atail-f.pl
DE2_NET/DE2_Board/system/DE2_Board_sim/contents_file_warning.txt
DE2_NET/DE2_Board/system/DE2_Board_sim/jtag_uart_0_input_mutex.dat
DE2_NET/DE2_Board/system/DE2_Board_sim/jtag_uart_0_input_stream.dat
DE2_NET/DE2_Board/system/DE2_Board_sim/jtag_uart_0_output_stream.dat
DE2_NET/DE2_Board/system/DE2_Board_top.bdf
DE2_NET/DE2_Board/system/delay_reset_block.bdf
DE2_NET/DE2_Board/system/firmware_ROM.hex
DE2_NET/DE2_Board/system/firmware_ROM.v
DE2_NET/DE2_Board/system/jtag_uart_0.v
DE2_NET/DE2_Board/system/payload_buffer.hex
DE2_NET/DE2_Board/system/payload_buffer.v
DE2_NET/DE2_Board/system/reset_counter.v
DE2_NET/DE2_Board/system/rf_ram.mif
DE2_NET/DE2_Board/system/sopc_builder_debug_log.txt
DE2_NET/DE2_Board/system/sysid.v
DE2_NET/DE2_NET.dpf
DE2_NET/DE2_NET.pof
DE2_NET/DE2_NET.qpf
DE2_NET/DE2_NET.qsf
DE2_NET/DE2_NET.sof
DE2_NET/DE2_NET.v
DE2_NET/DM9000A/cb_generator.pl
DE2_NET/DM9000A/class.ptf
DE2_NET/DM9000A/hdl/DM9000A_IF.v
DE2_NET/DM9000A/inc/basic_io.h
DE2_NET/DM9000A/inc/DM9000A.C
DE2_NET/DM9000A/inc/DM9000A.H
DE2_NET/DM9000A.v
DE2_NET/DM9000A_IF.v
DE2_NET/epcs_controller.v
DE2_NET/epcs_controller_boot_rom.hex
DE2_NET/FIFO_16_256.v
DE2_NET/hello_led_0/.cdtbuild
DE2_NET/hello
DE2_NET/.metadata/.plugins/org.eclipse.core.resources/.projects/hello_led_0/.properties
DE2_NET/.metadata/.plugins/org.eclipse.core.resources/.projects/hello_led_0_syslib/.properties
DE2_NET/.metadata/.plugins/org.eclipse.core.resources/.root/9.tree
DE2_NET/.metadata/.plugins/org.eclipse.core.resources/.safetable/org.eclipse.core.resources
DE2_NET/.metadata/.plugins/org.eclipse.core.runtime/.settings/org.eclipse.cdt.core.prefs
DE2_NET/.metadata/.plugins/org.eclipse.core.runtime/.settings/org.eclipse.cdt.debug.core.prefs
DE2_NET/.metadata/.plugins/org.eclipse.core.runtime/.settings/org.eclipse.cdt.ui.prefs
DE2_NET/.metadata/.plugins/org.eclipse.core.runtime/.settings/org.eclipse.team.cvs.ui.prefs
DE2_NET/.metadata/.plugins/org.eclipse.core.runtime/.settings/org.eclipse.team.ui.prefs
DE2_NET/.metadata/.plugins/org.eclipse.core.runtime/.settings/org.eclipse.ui.prefs
DE2_NET/.metadata/.plugins/org.eclipse.core.runtime/.settings/org.eclipse.ui.workbench.prefs
DE2_NET/.metadata/.plugins/org.eclipse.ui.workbench/dialog_settings.xml
DE2_NET/.metadata/.plugins/org.eclipse.ui.workbench/workbench.xml
DE2_NET/.metadata/version.ini
DE2_NET/.sopc_builder/install.ptf
DE2_NET/altpllpll_0.ppf
DE2_NET/Audio_0.v
DE2_NET/Audio_DAC_FIFO/cb_generator.pl
DE2_NET/Audio_DAC_FIFO/class.ptf
DE2_NET/Audio_DAC_FIFO/hdl/AUDIO_DAC_FIFO.v
DE2_NET/Audio_DAC_FIFO/hdl/FIFO_16_256.v
DE2_NET/AUDIO_DAC_FIFO.v
DE2_NET/Audio_PLL.ppf
DE2_NET/Audio_PLL.v
DE2_NET/bht_ram.mif
DE2_NET/Binary_VGA_Controller/cb_generator.pl
DE2_NET/Binary_VGA_Controller/class.ptf
DE2_NET/Binary_VGA_Controller/hdl/Img_DATA.hex
DE2_NET/Binary_VGA_Controller/hdl/Img_RAM.v
DE2_NET/Binary_VGA_Controller/hdl/VGA_Controller.v
DE2_NET/Binary_VGA_Controller/hdl/VGA_NIOS_CTRL.v
DE2_NET/Binary_VGA_Controller/hdl/VGA_OSD_RAM.v
DE2_NET/Binary_VGA_Controller/hdl/VGA_Param.h
DE2_NET/Binary_VGA_Controller/inc/VGA.c
DE2_NET/Binary_VGA_Controller/inc/VGA.h
DE2_NET/button_pio.v
DE2_NET/clock_0.v
DE2_NET/clock_1.v
DE2_NET/cpu_0.ocp
DE2_NET/cpu_0.v
DE2_NET/cpu_0.vo
DE2_NET/cpu_0_bht_ram.mif
DE2_NET/cpu_0_dc_tag_ram.mif
DE2_NET/cpu_0_ic_tag_ram.mif
DE2_NET/cpu_0_jtag_debug_module.v
DE2_NET/cpu_0_jtag_debug_module_wrapper.v
DE2_NET/cpu_0_mult_cell.v
DE2_NET/cpu_0_ociram_default_contents.mif
DE2_NET/cpu_0_rf_ram_a.mif
DE2_NET/cpu_0_rf_ram_b.mif
DE2_NET/cpu_0_test_bench.v
DE2_NET/dc_tag_ram.mif
DE2_NET/DE2_Board/class.ptf
DE2_NET/DE2_Board/system/.sopc_builder/install.ptf
DE2_NET/DE2_Board/system/asmi.v
DE2_NET/DE2_Board/system/cmp_state.ini
DE2_NET/DE2_Board/system/cpu_0.ocp
DE2_NET/DE2_Board/system/cpu_0.v
DE2_NET/DE2_Board/system/cpu_0_test_bench.v
DE2_NET/DE2_Board/system/data_RAM.hex
DE2_NET/DE2_Board/system/data_RAM.v
DE2_NET/DE2_Board/system/DE2_Board.asm.rpt
DE2_NET/DE2_Board/system/DE2_Board.bsf
DE2_NET/DE2_Board/system/DE2_Board.cdf
DE2_NET/DE2_Board/system/DE2_Board.done
DE2_NET/DE2_Board/system/DE2_Board.fit.eqn
DE2_NET/DE2_Board/system/DE2_Board.fit.rpt
DE2_NET/DE2_Board/system/DE2_Board.fit.summary
DE2_NET/DE2_Board/system/DE2_Board.flow.rpt
DE2_NET/DE2_Board/system/DE2_Board.map.eqn
DE2_NET/DE2_Board/system/DE2_Board.map.rpt
DE2_NET/DE2_Board/system/DE2_Board.map.summary
DE2_NET/DE2_Board/system/DE2_Board.pin
DE2_NET/DE2_Board/system/DE2_Board.pof
DE2_NET/DE2_Board/system/DE2_Board.ptf
DE2_NET/DE2_Board/system/DE2_Board.ptf.5.00
DE2_NET/DE2_Board/system/DE2_Board.ptf.bak
DE2_NET/DE2_Board/system/DE2_Board.qpf
DE2_NET/DE2_Board/system/DE2_Board.qsf
DE2_NET/DE2_Board/system/DE2_Board.qws
DE2_NET/DE2_Board/system/DE2_Board.sof
DE2_NET/DE2_Board/system/DE2_Board.tan.rpt
DE2_NET/DE2_Board/system/DE2_Board.tan.summary
DE2_NET/DE2_Board/system/DE2_Board.v
DE2_NET/DE2_Board/system/DE2_Board_assignment_defaults.qdf
DE2_NET/DE2_Board/system/DE2_Board_generation_script
DE2_NET/DE2_Board/system/DE2_Board_log.txt
DE2_NET/DE2_Board/system/DE2_Board_setup_quartus.tcl
DE2_NET/DE2_Board/system/DE2_Board_sim/atail-f.pl
DE2_NET/DE2_Board/system/DE2_Board_sim/contents_file_warning.txt
DE2_NET/DE2_Board/system/DE2_Board_sim/jtag_uart_0_input_mutex.dat
DE2_NET/DE2_Board/system/DE2_Board_sim/jtag_uart_0_input_stream.dat
DE2_NET/DE2_Board/system/DE2_Board_sim/jtag_uart_0_output_stream.dat
DE2_NET/DE2_Board/system/DE2_Board_top.bdf
DE2_NET/DE2_Board/system/delay_reset_block.bdf
DE2_NET/DE2_Board/system/firmware_ROM.hex
DE2_NET/DE2_Board/system/firmware_ROM.v
DE2_NET/DE2_Board/system/jtag_uart_0.v
DE2_NET/DE2_Board/system/payload_buffer.hex
DE2_NET/DE2_Board/system/payload_buffer.v
DE2_NET/DE2_Board/system/reset_counter.v
DE2_NET/DE2_Board/system/rf_ram.mif
DE2_NET/DE2_Board/system/sopc_builder_debug_log.txt
DE2_NET/DE2_Board/system/sysid.v
DE2_NET/DE2_NET.dpf
DE2_NET/DE2_NET.pof
DE2_NET/DE2_NET.qpf
DE2_NET/DE2_NET.qsf
DE2_NET/DE2_NET.sof
DE2_NET/DE2_NET.v
DE2_NET/DM9000A/cb_generator.pl
DE2_NET/DM9000A/class.ptf
DE2_NET/DM9000A/hdl/DM9000A_IF.v
DE2_NET/DM9000A/inc/basic_io.h
DE2_NET/DM9000A/inc/DM9000A.C
DE2_NET/DM9000A/inc/DM9000A.H
DE2_NET/DM9000A.v
DE2_NET/DM9000A_IF.v
DE2_NET/epcs_controller.v
DE2_NET/epcs_controller_boot_rom.hex
DE2_NET/FIFO_16_256.v
DE2_NET/hello_led_0/.cdtbuild
DE2_NET/hello
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