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文件名称:DE2_70_NIOS_10_flash

  • 所属分类：
    VHDL-FPGA-Verilog
  • 标签属性：
    [MacOS] [C/C++] [源码]
  • 上传时间：
    2012-11-16
  • 文件大小：
    1.55mb
  • 已下载：
    0次
  • 提 供 者：
    boy****
  • 相关连接：
    无
  • 下载说明：
    别用迅雷下载，失败请重下，重下不扣分！
修正介绍说明

介绍说明－－下载内容来自于网络，使用问题请自行百度

首先将此Verilog程序下载到DE2-70开发板上后，然后用NiosII软件将任何文件的二进制数据写入到ssram或者sdram等存储器重去，并可以指定起始地址。-First program this Verilog downloaded to the DE2-70 development board, and then the use NiosII software binary data of any file written to memory such as ssram or sdram weight go, and you can specify a starting address.
(系统自动生成,下载前可以参看下载内容)

下载文件列表

DE2_70_NIOS_10_flash/
DE2_70_NIOS_10_flash/.sopc_builder/
DE2_70_NIOS_10_flash/.sopc_builder/install.ptf
DE2_70_NIOS_10_flash/.sopc_builder/install2.ptf
DE2_70_NIOS_10_flash/.sopc_builder/preferences.xml
DE2_70_NIOS_10_flash/AUDIO.v
DE2_70_NIOS_10_flash/DE2_70.qpf
DE2_70_NIOS_10_flash/DE2_70.qsf
DE2_70_NIOS_10_flash/DE2_70.qws
DE2_70_NIOS_10_flash/DE2_70_SOPC_sim/
DE2_70_NIOS_10_flash/DE2_70_SOPC_sim/atail-f.pl
DE2_70_NIOS_10_flash/DE2_70_SOPC_sim/contents_file_warning.txt
DE2_70_NIOS_10_flash/DE2_70_SOPC_sim/dummy_file
DE2_70_NIOS_10_flash/DE2_70_SOPC_sim/jtag_uart_input_mutex.dat
DE2_70_NIOS_10_flash/DE2_70_SOPC_sim/jtag_uart_input_stream.dat
DE2_70_NIOS_10_flash/DE2_70_SOPC_sim/jtag_uart_output_stream.dat
DE2_70_NIOS_10_flash/DE2_70_SOPC_sim/uart_input_data_mutex.dat
DE2_70_NIOS_10_flash/DE2_70_SOPC_sim/uart_input_data_stream.dat
DE2_70_NIOS_10_flash/DE2_70_SOPC_sim/uart_log_module.txt
DE2_70_NIOS_10_flash/DM9000A.v
DE2_70_NIOS_10_flash/IP/
DE2_70_NIOS_10_flash/IP/TERASIC_AUDIO/
DE2_70_NIOS_10_flash/IP/TERASIC_AUDIO/hdl/
DE2_70_NIOS_10_flash/IP/TERASIC_AUDIO/hdl/AUDIO_ADC.v
DE2_70_NIOS_10_flash/IP/TERASIC_AUDIO/hdl/AUDIO_DAC.v
DE2_70_NIOS_10_flash/IP/TERASIC_AUDIO/hdl/AUDIO_IF.v
DE2_70_NIOS_10_flash/IP/TERASIC_AUDIO/hdl/AUDIO_IF.v.bak
DE2_70_NIOS_10_flash/IP/TERASIC_AUDIO/hdl/AUDIO_IF_hw.tcl
DE2_70_NIOS_10_flash/IP/TERASIC_AUDIO/hdl/audio_fifo.v
DE2_70_NIOS_10_flash/IP/TERASIC_AUDIO/hdl/audio_fifo_wave0.jpg
DE2_70_NIOS_10_flash/IP/TERASIC_AUDIO/hdl/audio_fifo_wave1.jpg
DE2_70_NIOS_10_flash/IP/TERASIC_AUDIO/hdl/audio_fifo_waveforms.html
DE2_70_NIOS_10_flash/IP/TERASIC_AUDIO/software/
DE2_70_NIOS_10_flash/IP/TERASIC_AUDIO/software/AUDIO.c
DE2_70_NIOS_10_flash/IP/TERASIC_AUDIO/software/AUDIO.h
DE2_70_NIOS_10_flash/IP/TERASIC_AUDIO/software/AUDIO_REG.h
DE2_70_NIOS_10_flash/IP/TERASIC_Binary_VGA_Controller/
DE2_70_NIOS_10_flash/IP/TERASIC_Binary_VGA_Controller/hdl/
DE2_70_NIOS_10_flash/IP/TERASIC_Binary_VGA_Controller/hdl/Binary_VGA_Control_IF_hw.tcl
DE2_70_NIOS_10_flash/IP/TERASIC_Binary_VGA_Controller/hdl/Binary_VGA_Control_IF_hw.tcl~
DE2_70_NIOS_10_flash/IP/TERASIC_Binary_VGA_Controller/hdl/Img_DATA.hex
DE2_70_NIOS_10_flash/IP/TERASIC_Binary_VGA_Controller/hdl/Img_RAM.v
DE2_70_NIOS_10_flash/IP/TERASIC_Binary_VGA_Controller/hdl/VGA_Controller.v
DE2_70_NIOS_10_flash/IP/TERASIC_Binary_VGA_Controller/hdl/VGA_NIOS_CTRL.v
DE2_70_NIOS_10_flash/IP/TERASIC_Binary_VGA_Controller/hdl/VGA_NIOS_CTRL.v.bak
DE2_70_NIOS_10_flash/IP/TERASIC_Binary_VGA_Controller/hdl/VGA_OSD_RAM.v
DE2_70_NIOS_10_flash/IP/TERASIC_Binary_VGA_Controller/hdl/VGA_Param.h
DE2_70_NIOS_10_flash/IP/TERASIC_Binary_VGA_Controller/software/
DE2_70_NIOS_10_flash/IP/TERASIC_DM9000A/
DE2_70_NIOS_10_flash/IP/TERASIC_DM9000A/hdl/
DE2_70_NIOS_10_flash/IP/TERASIC_DM9000A/hdl/DM9000A_IF.v
DE2_70_NIOS_10_flash/IP/TERASIC_DM9000A/hdl/DM9000A_IF_hw.tcl
DE2_70_NIOS_10_flash/IP/TERASIC_DM9000A/hdl/DM9000A_IF_hw.tcl~
DE2_70_NIOS_10_flash/IP/TERASIC_DM9000A/software/
DE2_70_NIOS_10_flash/IP/TERASIC_DM9000A/software/DM9000A.C
DE2_70_NIOS_10_flash/IP/TERASIC_DM9000A/software/DM9000A.H
DE2_70_NIOS_10_flash/IP/TERASIC_ISP1362/
DE2_70_NIOS_10_flash/IP/TERASIC_ISP1362/hdl/
DE2_70_NIOS_10_flash/IP/TERASIC_ISP1362/hdl/ISP1362_IF.v
DE2_70_NIOS_10_flash/IP/TERASIC_ISP1362/hdl/ISP1362_IF_hw.tcl
DE2_70_NIOS_10_flash/IP/TERASIC_ISP1362/software/
DE2_70_NIOS_10_flash/IP/TERASIC_SEG7/
DE2_70_NIOS_10_flash/IP/TERASIC_SEG7/hdl/
DE2_70_NIOS_10_flash/IP/TERASIC_SEG7/hdl/SEG7_IF.v
DE2_70_NIOS_10_flash/IP/TERASIC_SEG7/hdl/SEG7_IF_hw.tcl
DE2_70_NIOS_10_flash/IP/TERASIC_SEG7/software/
DE2_70_NIOS_10_flash/IP/TERASIC_SEG7/software/SEG7.c
DE2_70_NIOS_10_flash/IP/TERASIC_SEG7/software/SEG7.h
DE2_70_NIOS_10_flash/ISP1362.v
DE2_70_NIOS_10_flash/SEG7.v
DE2_70_NIOS_10_flash/VGA.v
DE2_70_NIOS_10_flash/altpllpll.ppf
DE2_70_NIOS_10_flash/altpllpll.qip
DE2_70_NIOS_10_flash/altpllpll.v
DE2_70_NIOS_10_flash/cpu.ocp
DE2_70_NIOS_10_flash/cpu.sdc
DE2_70_NIOS_10_flash/cpu.v
DE2_70_NIOS_10_flash/cpu_bht_ram.mif
DE2_70_NIOS_10_flash/cpu_dc_tag_ram.mif
DE2_70_NIOS_10_flash/cpu_ic_tag_ram.mif
DE2_70_NIOS_10_flash/cpu_jtag_debug_module_sysclk.v
DE2_70_NIOS_10_flash/cpu_jtag_debug_module_tck.v
DE2_70_NIOS_10_flash/cpu_jtag_debug_module_wrapper.v
DE2_70_NIOS_10_flash/cpu_mult_cell.v
DE2_70_NIOS_10_flash/cpu_ociram_default_contents.mif
DE2_70_NIOS_10_flash/cpu_rf_ram_a.mif
DE2_70_NIOS_10_flash/cpu_rf_ram_b.mif
DE2_70_NIOS_10_flash/cpu_test_bench.v
DE2_70_NIOS_10_flash/db/
DE2_70_NIOS_10_flash/hardware/
DE2_70_NIOS_10_flash/hardware/DE2_70_NIOS.v
DE2_70_NIOS_10_flash/hardware/Reset_Delay.v
DE2_70_NIOS_10_flash/i2c_sclk.v
DE2_70_NIOS_10_flash/i2c_sdat.v
DE2_70_NIOS_10_flash/jtag_uart.v
DE2_70_NIOS_10_flash/lcd.v
DE2_70_NIOS_10_flash/nios_ii.bsf
DE2_70_NIOS_10_flash/nios_ii.ptf
DE2_70_NIOS_10_flash/nios_ii.ptf.bak
DE2_70_NIOS_10_flash/nios_ii.ptf.pre_generation_ptf
DE2_70_NIOS_10_flash/nios_ii.qip
DE2_70_NIOS_10_flash/nios_ii.sopc
DE2_70_NIOS_10_flash/nios_ii.sopcinfo
DE2_70_NIOS_10_flash/nios_ii.v
DE2_70_NIOS_10_flash/nios_ii_clock_0.v
DE2_70_NIOS_10_flash/nios_ii_clock_1.v
DE2_70_NIOS_10_flash/nios_ii_generation_script
DE2_70_NIOS_1

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