文件名称:8.4-ADC0809-
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基于VHDL语言，实现对ADC0809简单控制,ADC0809没有内部时钟，需外接10KHz~1290Hz的时钟信号，这里由FPGA的系
--统时钟（50MHz）经256分频得到clk1（195KHz）作为ADC0809转换工作时钟。
-Based on VHDL ADC0809 simple control, ADC0809 no internal clock, an external clock signal of 10KHz ~ 1290Hz here by the Department of the FPGA- the system clock (50MHz) frequency to be at 256 points the clk1 (195KHz) as the ADC0809 conversion work clock .
--统时钟（50MHz）经256分频得到clk1（195KHz）作为ADC0809转换工作时钟。
-Based on VHDL ADC0809 simple control, ADC0809 no internal clock, an external clock signal of 10KHz ~ 1290Hz here by the Department of the FPGA- the system clock (50MHz) frequency to be at 256 points the clk1 (195KHz) as the ADC0809 conversion work clock .
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8.4 ADC0809 VHDL控制程序.doc
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