文件名称:NandController(lattice)
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NAND Flash控制器源码 Verilog-NAND Flash controller source Verilog
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下载文件列表
NandController(lattice)/doc/rd1055.pdf
NandController(lattice)/doc/rd1055_readme.txt
NandController(lattice)/project/nand_flash_cntl.lpf
NandController(lattice)/project/nfcm_tb_vhd.udo_example
NandController(lattice)/simulation/verilog/rtl_verilog.do
NandController(lattice)/simulation/verilog/timing_verilog.do
NandController(lattice)/simulation/vhdl/rtl_vhdl.do
NandController(lattice)/simulation/vhdl/timing_vhdl.do
NandController(lattice)/source/verilog/ACounter.v
NandController(lattice)/source/verilog/ErrLoc.v
NandController(lattice)/source/verilog/H_gen.v
NandController(lattice)/source/verilog/ipexpress/xo/ebr_buffer.lpc
NandController(lattice)/source/verilog/ipexpress/xo/ebr_buffer.v
NandController(lattice)/source/verilog/ipexpress/xo2/ebr_buffer.lpc
NandController(lattice)/source/verilog/ipexpress/xo2/ebr_buffer.v
NandController(lattice)/source/verilog/ipexpress/xp2/ebr_buffer.lpc
NandController(lattice)/source/verilog/ipexpress/xp2/ebr_buffer.v
NandController(lattice)/source/verilog/MFSM.v
NandController(lattice)/source/verilog/nfcm_top.v
NandController(lattice)/source/verilog/nfcm_top.vhd
NandController(lattice)/source/verilog/TFSM.v
NandController(lattice)/source/vhdl/ACounter.vhd
NandController(lattice)/source/vhdl/ErrLoc.vhd
NandController(lattice)/source/vhdl/H_gen.vhd
NandController(lattice)/source/vhdl/ipexpress/xo/ebr_buffer.lpc
NandController(lattice)/source/vhdl/ipexpress/xo/ebr_buffer.vhd
NandController(lattice)/source/vhdl/ipexpress/xo2/ebr_buffer.lpc
NandController(lattice)/source/vhdl/ipexpress/xo2/ebr_buffer.vhd
NandController(lattice)/source/vhdl/ipexpress/xp2/ebr_buffer.lpc
NandController(lattice)/source/vhdl/ipexpress/xp2/ebr_buffer.vhd
NandController(lattice)/source/vhdl/MFSM.vhd
NandController(lattice)/source/vhdl/nfcm_top.vhd
NandController(lattice)/source/vhdl/TFSM.vhd
NandController(lattice)/testbench/verilog/flash_interface.v
NandController(lattice)/testbench/verilog/nfcm_tb.v
NandController(lattice)/testbench/vhdl/flash_interface.vhd
NandController(lattice)/testbench/vhdl/nfcm_tb.vhd
NandController(lattice)/source/verilog/ipexpress/xo
NandController(lattice)/source/verilog/ipexpress/xo2
NandController(lattice)/source/verilog/ipexpress/xp2
NandController(lattice)/source/vhdl/ipexpress/xo
NandController(lattice)/source/vhdl/ipexpress/xo2
NandController(lattice)/source/vhdl/ipexpress/xp2
NandController(lattice)/source/verilog/ipexpress
NandController(lattice)/source/vhdl/ipexpress
NandController(lattice)/simulation/verilog
NandController(lattice)/simulation/vhdl
NandController(lattice)/source/verilog
NandController(lattice)/source/vhdl
NandController(lattice)/testbench/verilog
NandController(lattice)/testbench/vhdl
NandController(lattice)/doc
NandController(lattice)/project
NandController(lattice)/simulation
NandController(lattice)/source
NandController(lattice)/testbench
NandController(lattice)
NandController(lattice)/doc/rd1055_readme.txt
NandController(lattice)/project/nand_flash_cntl.lpf
NandController(lattice)/project/nfcm_tb_vhd.udo_example
NandController(lattice)/simulation/verilog/rtl_verilog.do
NandController(lattice)/simulation/verilog/timing_verilog.do
NandController(lattice)/simulation/vhdl/rtl_vhdl.do
NandController(lattice)/simulation/vhdl/timing_vhdl.do
NandController(lattice)/source/verilog/ACounter.v
NandController(lattice)/source/verilog/ErrLoc.v
NandController(lattice)/source/verilog/H_gen.v
NandController(lattice)/source/verilog/ipexpress/xo/ebr_buffer.lpc
NandController(lattice)/source/verilog/ipexpress/xo/ebr_buffer.v
NandController(lattice)/source/verilog/ipexpress/xo2/ebr_buffer.lpc
NandController(lattice)/source/verilog/ipexpress/xo2/ebr_buffer.v
NandController(lattice)/source/verilog/ipexpress/xp2/ebr_buffer.lpc
NandController(lattice)/source/verilog/ipexpress/xp2/ebr_buffer.v
NandController(lattice)/source/verilog/MFSM.v
NandController(lattice)/source/verilog/nfcm_top.v
NandController(lattice)/source/verilog/nfcm_top.vhd
NandController(lattice)/source/verilog/TFSM.v
NandController(lattice)/source/vhdl/ACounter.vhd
NandController(lattice)/source/vhdl/ErrLoc.vhd
NandController(lattice)/source/vhdl/H_gen.vhd
NandController(lattice)/source/vhdl/ipexpress/xo/ebr_buffer.lpc
NandController(lattice)/source/vhdl/ipexpress/xo/ebr_buffer.vhd
NandController(lattice)/source/vhdl/ipexpress/xo2/ebr_buffer.lpc
NandController(lattice)/source/vhdl/ipexpress/xo2/ebr_buffer.vhd
NandController(lattice)/source/vhdl/ipexpress/xp2/ebr_buffer.lpc
NandController(lattice)/source/vhdl/ipexpress/xp2/ebr_buffer.vhd
NandController(lattice)/source/vhdl/MFSM.vhd
NandController(lattice)/source/vhdl/nfcm_top.vhd
NandController(lattice)/source/vhdl/TFSM.vhd
NandController(lattice)/testbench/verilog/flash_interface.v
NandController(lattice)/testbench/verilog/nfcm_tb.v
NandController(lattice)/testbench/vhdl/flash_interface.vhd
NandController(lattice)/testbench/vhdl/nfcm_tb.vhd
NandController(lattice)/source/verilog/ipexpress/xo
NandController(lattice)/source/verilog/ipexpress/xo2
NandController(lattice)/source/verilog/ipexpress/xp2
NandController(lattice)/source/vhdl/ipexpress/xo
NandController(lattice)/source/vhdl/ipexpress/xo2
NandController(lattice)/source/vhdl/ipexpress/xp2
NandController(lattice)/source/verilog/ipexpress
NandController(lattice)/source/vhdl/ipexpress
NandController(lattice)/simulation/verilog
NandController(lattice)/simulation/vhdl
NandController(lattice)/source/verilog
NandController(lattice)/source/vhdl
NandController(lattice)/testbench/verilog
NandController(lattice)/testbench/vhdl
NandController(lattice)/doc
NandController(lattice)/project
NandController(lattice)/simulation
NandController(lattice)/source
NandController(lattice)/testbench
NandController(lattice)
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