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文件名称:ex2

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  • 上传时间:
    2012-11-16
  • 文件大小:
    468.09kb
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介绍说明--下载内容来自于网络,使用问题请自行百度

FPGA数码管显示,带自动计数器,开发板实例教程-The FPGA digital display with automatic counter, the development board tutorial examples
(系统自动生成,下载前可以参看下载内容)

下载文件列表

ex2/
ex2/seg7_verilog/
ex2/seg7_verilog/db/
ex2/seg7_verilog/db/prev_cmp_seg7.asm.qmsg
ex2/seg7_verilog/db/prev_cmp_seg7.eda.qmsg
ex2/seg7_verilog/db/prev_cmp_seg7.fit.qmsg
ex2/seg7_verilog/db/prev_cmp_seg7.map.qmsg
ex2/seg7_verilog/db/prev_cmp_seg7.qmsg
ex2/seg7_verilog/db/prev_cmp_seg7.sta.qmsg
ex2/seg7_verilog/db/prev_cmp_seg7.tan.qmsg
ex2/seg7_verilog/db/seg7.db_info
ex2/seg7_verilog/db/seg7.sld_design_entry.sci
ex2/seg7_verilog/db/seg7_global_asgn_op.abo
ex2/seg7_verilog/incremental_db/
ex2/seg7_verilog/incremental_db/compiled_partitions/
ex2/seg7_verilog/incremental_db/compiled_partitions/seg7.db_info
ex2/seg7_verilog/incremental_db/compiled_partitions/seg7.root_partition.cmp.atm
ex2/seg7_verilog/incremental_db/compiled_partitions/seg7.root_partition.cmp.dfp
ex2/seg7_verilog/incremental_db/compiled_partitions/seg7.root_partition.cmp.hdbx
ex2/seg7_verilog/incremental_db/compiled_partitions/seg7.root_partition.cmp.kpt
ex2/seg7_verilog/incremental_db/compiled_partitions/seg7.root_partition.cmp.logdb
ex2/seg7_verilog/incremental_db/compiled_partitions/seg7.root_partition.cmp.rcf
ex2/seg7_verilog/incremental_db/compiled_partitions/seg7.root_partition.map.atm
ex2/seg7_verilog/incremental_db/compiled_partitions/seg7.root_partition.map.dpi
ex2/seg7_verilog/incremental_db/compiled_partitions/seg7.root_partition.map.hdbx
ex2/seg7_verilog/incremental_db/compiled_partitions/seg7.root_partition.map.kpt
ex2/seg7_verilog/incremental_db/README
ex2/seg7_verilog/seg7.asm.rpt
ex2/seg7_verilog/seg7.bsf
ex2/seg7_verilog/seg7.cdf
ex2/seg7_verilog/seg7.done
ex2/seg7_verilog/seg7.dpf
ex2/seg7_verilog/seg7.eda.rpt
ex2/seg7_verilog/seg7.fit.rpt
ex2/seg7_verilog/seg7.fit.smsg
ex2/seg7_verilog/seg7.fit.summary
ex2/seg7_verilog/seg7.flow.rpt
ex2/seg7_verilog/seg7.map.rpt
ex2/seg7_verilog/seg7.map.summary
ex2/seg7_verilog/seg7.pin
ex2/seg7_verilog/seg7.pof
ex2/seg7_verilog/seg7.qpf
ex2/seg7_verilog/seg7.qsf
ex2/seg7_verilog/seg7.qws
ex2/seg7_verilog/seg7.sdc
ex2/seg7_verilog/seg7.sof
ex2/seg7_verilog/seg7.sta.rpt
ex2/seg7_verilog/seg7.sta.summary
ex2/seg7_verilog/seg7.tan.rpt
ex2/seg7_verilog/seg7.tan.summary
ex2/seg7_verilog/seg7.v
ex2/seg7_verilog/seg7.v.bak
ex2/seg7_verilog/seg7_assignment_defaults.qdf
ex2/seg7_verilog/seg7_nativelink_simulation.rpt
ex2/seg7_verilog/simulation/
ex2/seg7_verilog/simulation/modelsim/
ex2/seg7_verilog/simulation/modelsim/altera_mf.v
ex2/seg7_verilog/simulation/modelsim/cyclone_atoms.v
ex2/seg7_verilog/simulation/modelsim/print_task.v
ex2/seg7_verilog/simulation/modelsim/seg7.sft
ex2/seg7_verilog/simulation/modelsim/seg7.vo
ex2/seg7_verilog/simulation/modelsim/seg7_modelsim.xrf
ex2/seg7_verilog/simulation/modelsim/seg7_v.sdo
ex2/seg7_verilog/sopc_builder_log.txt

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