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The purpose of this lab is to introduce the concept of FSMs with a datapath, and to
study the usage of more complex test benches. Also, we enforce a rudimentary design
methodology by assuming that the students are part of a bigger project, and have no
knowledge of VHDL-implementation of the datapath (made by a hypothetical other
group) other than its predefined Entity Interface until they come to the lab.
The rest of this document is structured as follows: Section 2 describes some prelimi-
nary reading and exercises that should be done before the lab. Section 3 details the
design tasks that should be carried out to pass this lab.
study the usage of more complex test benches. Also, we enforce a rudimentary design
methodology by assuming that the students are part of a bigger project, and have no
knowledge of VHDL-implementation of the datapath (made by a hypothetical other
group) other than its predefined Entity Interface until they come to the lab.
The rest of this document is structured as follows: Section 2 describes some prelimi-
nary reading and exercises that should be done before the lab. Section 3 details the
design tasks that should be carried out to pass this lab.
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下载文件列表
xx_new4/work/_info
xx_new4/work/alu/_primary.dat
xx_new4/work/alu/behaviour.dat
xx_new4/work/alu/behaviour.asm
xx_new4/work/alu
xx_new4/work/package_microassemblycode/_primary.dat
xx_new4/work/package_microassemblycode/_vhdl.asm
xx_new4/work/package_microassemblycode
xx_new4/work/regfile/_primary.dat
xx_new4/work/regfile/behaviour.dat
xx_new4/work/regfile/behaviour.asm
xx_new4/work/regfile
xx_new4/work/selector/_primary.dat
xx_new4/work/selector/behaviour.dat
xx_new4/work/selector/behaviour.asm
xx_new4/work/selector
xx_new4/work/shifter/_primary.dat
xx_new4/work/shifter/behaviour.dat
xx_new4/work/shifter/behaviour.asm
xx_new4/work/shifter
xx_new4/work/videocomposer/_primary.dat
xx_new4/work/videocomposer/composite.dat
xx_new4/work/videocomposer/composite.asm
xx_new4/work/videocomposer
xx_new4/work/videocomposer_fpga/_primary.dat
xx_new4/work/videocomposer_fpga/behaviour.dat
xx_new4/work/videocomposer_fpga/behaviour.asm
xx_new4/work/videocomposer_fpga
xx_new4/work/datapath/_primary.dat
xx_new4/work/datapath/behaviour.dat
xx_new4/work/datapath/behaviour.asm
xx_new4/work/datapath
xx_new4/work/single_port_rom/_primary.dat
xx_new4/work/single_port_rom/syn.dat
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xx_new4/work/tb_videocomposer_93/tb_behaviour.asm
xx_new4/work/tb_videocomposer_93
xx_new4/work
xx_new4/videoComposer_fpga.vhd
xx_new4/alu.vhd
xx_new4/dataPath.vhd
xx_new4/package_microAssemblyCode.vhd
xx_new4/regFile.vhd
xx_new4/selector.vhd
xx_new4/shifter.vhd
xx_new4/single_port_rom.vhd
xx_new4/tb_videoComposer_93.vhd
xx_new4/videocomposer.vhd
xx_new4/lpm/_info
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xx_new4/lpm/lpm_device_families/_primary.dat
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xx_new4/work/selector/behaviour.asm
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xx_new4/work/shifter/_primary.dat
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xx_new4/selector.vhd
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xx_new4/videocomposer.vhd
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