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文件名称:the_design_basedonfpga

  • 所属分类：
    VHDL-FPGA-Verilog
  • 标签属性：
    [HTML]
  • 上传时间：
    2012-11-16
  • 文件大小：
    562.64kb
  • 已下载：
    0次
  • 提 供 者：
    丁****
  • 相关连接：
    无
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修正介绍说明

介绍说明－－下载内容来自于网络，使用问题请自行百度

1. clkdiv 介绍时钟分频器的建模

2. counter 介绍计数的建模

3. dtrig 介绍D触发器的建模

4. jktrig 介绍JK触发器的建模

5. shiftreg 介绍移位寄存器的建模

6. ttrig 介绍T触发器的建模-The 1. Clkdiv modeling clock divider 2. Counter introduced count modeling the The 3. Dtrig 4. Jktrig introduce the modeling of the JK flip-flop 5 introduces the D flip-flop modeling. Shiftreg introduces the modeling of shift register 6 the. ttrig T trigger modeling
(系统自动生成,下载前可以参看下载内容)

下载文件列表

the_design_of_clkdiv_counter_dtrig_jktrig_shiftreg_ttrig_based_on_fpga/readme.txt
the_design_of_clkdiv_counter_dtrig_jktrig_shiftreg_ttrig_based_on_fpga/readme.txt.bak
the_design_of_clkdiv_counter_dtrig_jktrig_shiftreg_ttrig_based_on_fpga/ttrig/ttrig.done
the_design_of_clkdiv_counter_dtrig_jktrig_shiftreg_ttrig_based_on_fpga/ttrig/ttrig.flow.rpt
the_design_of_clkdiv_counter_dtrig_jktrig_shiftreg_ttrig_based_on_fpga/ttrig/ttrig.map.rpt
the_design_of_clkdiv_counter_dtrig_jktrig_shiftreg_ttrig_based_on_fpga/ttrig/ttrig.map.summary
the_design_of_clkdiv_counter_dtrig_jktrig_shiftreg_ttrig_based_on_fpga/ttrig/ttrig.qpf
the_design_of_clkdiv_counter_dtrig_jktrig_shiftreg_ttrig_based_on_fpga/ttrig/ttrig.qsf
the_design_of_clkdiv_counter_dtrig_jktrig_shiftreg_ttrig_based_on_fpga/ttrig/ttrig.qws
the_design_of_clkdiv_counter_dtrig_jktrig_shiftreg_ttrig_based_on_fpga/ttrig/ttrig.sim.rpt
the_design_of_clkdiv_counter_dtrig_jktrig_shiftreg_ttrig_based_on_fpga/ttrig/ttrig.vhd
the_design_of_clkdiv_counter_dtrig_jktrig_shiftreg_ttrig_based_on_fpga/ttrig/ttrig.vwf
the_design_of_clkdiv_counter_dtrig_jktrig_shiftreg_ttrig_based_on_fpga/ttrig/incremental_db/README
the_design_of_clkdiv_counter_dtrig_jktrig_shiftreg_ttrig_based_on_fpga/ttrig/incremental_db/compiled_partitions/ttrig.root_partition.map.atm
the_design_of_clkdiv_counter_dtrig_jktrig_shiftreg_ttrig_based_on_fpga/ttrig/incremental_db/compiled_partitions/ttrig.root_partition.map.dpi
the_design_of_clkdiv_counter_dtrig_jktrig_shiftreg_ttrig_based_on_fpga/ttrig/incremental_db/compiled_partitions/ttrig.root_partition.map.hdbx
the_design_of_clkdiv_counter_dtrig_jktrig_shiftreg_ttrig_based_on_fpga/ttrig/incremental_db/compiled_partitions/ttrig.root_partition.map.kpt
the_design_of_clkdiv_counter_dtrig_jktrig_shiftreg_ttrig_based_on_fpga/ttrig/db/prev_cmp_ttrig.map.qmsg
the_design_of_clkdiv_counter_dtrig_jktrig_shiftreg_ttrig_based_on_fpga/ttrig/db/prev_cmp_ttrig.qmsg
the_design_of_clkdiv_counter_dtrig_jktrig_shiftreg_ttrig_based_on_fpga/ttrig/db/ttrig.(0).cnf.cdb
the_design_of_clkdiv_counter_dtrig_jktrig_shiftreg_ttrig_based_on_fpga/ttrig/db/ttrig.(0).cnf.hdb
the_design_of_clkdiv_counter_dtrig_jktrig_shiftreg_ttrig_based_on_fpga/ttrig/db/ttrig.cbx.xml
the_design_of_clkdiv_counter_dtrig_jktrig_shiftreg_ttrig_based_on_fpga/ttrig/db/ttrig.cmp.rdb
the_design_of_clkdiv_counter_dtrig_jktrig_shiftreg_ttrig_based_on_fpga/ttrig/db/ttrig.cmp_merge.kpt
the_design_of_clkdiv_counter_dtrig_jktrig_shiftreg_ttrig_based_on_fpga/ttrig/db/ttrig.db_info
the_design_of_clkdiv_counter_dtrig_jktrig_shiftreg_ttrig_based_on_fpga/ttrig/db/ttrig.eco.cdb
the_design_of_clkdiv_counter_dtrig_jktrig_shiftreg_ttrig_based_on_fpga/ttrig/db/ttrig.eds_overflow
the_design_of_clkdiv_counter_dtrig_jktrig_shiftreg_ttrig_based_on_fpga/ttrig/db/ttrig.fnsim.cdb
the_design_of_clkdiv_counter_dtrig_jktrig_shiftreg_ttrig_based_on_fpga/ttrig/db/ttrig.fnsim.hdb
the_design_of_clkdiv_counter_dtrig_jktrig_shiftreg_ttrig_based_on_fpga/ttrig/db/ttrig.fnsim.qmsg
the_design_of_clkdiv_counter_dtrig_jktrig_shiftreg_ttrig_based_on_fpga/ttrig/db/ttrig.hier_info
the_design_of_clkdiv_counter_dtrig_jktrig_shiftreg_ttrig_based_on_fpga/ttrig/db/ttrig.hif
the_design_of_clkdiv_counter_dtrig_jktrig_shiftreg_ttrig_based_on_fpga/ttrig/db/ttrig.lpc.html
the_design_of_clkdiv_counter_dtrig_jktrig_shiftreg_ttrig_based_on_fpga/ttrig/db/ttrig.lpc.rdb
the_design_of_clkdiv_counter_dtrig_jktrig_shiftreg_ttrig_based_on_fpga/ttrig/db/ttrig.lpc.txt
the_design_of_clkdiv_counter_dtrig_jktrig_shiftreg_ttrig_based_on_fpga/ttrig/db/ttrig.map.bpm
the_design_of_clkdiv_counter_dtrig_jktrig_shiftreg_ttrig_based_on_fpga/ttrig/db/ttrig.map.cdb
the_design_of_clkdiv_counter_dtrig_jktrig_shiftreg_ttrig_based_on_fpga/ttrig/db/ttrig.map.ecobp
the_design_of_clkdiv_counter_dtrig_jktrig_shiftreg_ttrig_based_on_fpga/ttrig/db/ttrig.map.hdb
the_design_of_clkdiv_counter_dtrig_jktrig_shiftreg_ttrig_based_on_fpga/ttrig/db/ttrig.map.kpt
the_design_of_clkdiv_counter_dtrig_jktrig_shiftreg_ttrig_based_on_fpga/ttrig/db/ttrig.map.logdb
the_design_of_clkdiv_counter_dtrig_jktrig_shiftreg_ttrig_based_on_fpga/ttrig/db/ttrig.map.qmsg
the_design_of_clkdiv_counter_dtrig_jktrig_shiftreg_ttrig_based_on_fpga/ttrig/db/ttrig.map_bb.cdb
the_design_of_clkdiv_counter_dtrig_jktrig_shiftreg_ttrig_based_on_fpga/ttrig/db/ttrig.map_bb.hdb
the_design_of_clkdiv_counter_dtrig_jktrig_shiftreg_ttrig_based_on_fpga/ttrig/db/ttrig.map_bb.logdb
the_design_of_clkdiv_counter_dtrig_jktrig_shiftreg_ttrig_based_on_fpga/ttrig/db/ttrig.pre_map.cdb
the_design_of_clkdiv_counter_dtrig_jktrig_shiftreg_ttrig_based_on_fpga/ttrig/db/ttrig.pre_map.hdb
the_design_of_clkdiv_counter_dtrig_jktrig_shiftreg_ttrig_based_on_fpga/ttrig/db/ttrig.rtlv.hdb
the_design_of_clkdiv_counter_dtrig_jktrig_shiftreg_ttrig_based_on_fpga/ttrig/db/ttrig.rtlv_sg.cdb
the_design_of_clkdiv_counter_dtrig_jktrig_shiftreg_ttrig_based_on_fpga/ttrig/db/ttrig.rtlv_sg_swap.cdb
the_design_of_clkdiv_counter_dtrig_jktrig_shiftreg_ttrig_based_on_fpga/ttrig/db/ttrig.sgdiff.cdb
the_design_of_clkdiv_counter_dtrig_jktrig_shiftreg_ttrig_based_on_fpga/ttrig/db/ttrig.sgdiff.hdb
the_design_of_clkdiv_

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