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文件名称:clk

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  • 上传时间:
    2012-11-16
  • 文件大小:
    326.88kb
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    0次
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    别用迅雷下载,失败请重下,重下不扣分!

介绍说明--下载内容来自于网络,使用问题请自行百度

基于EP2C5Q208C的二分频verilog代码,modelsim仿真及下载配置-Verilog code, modelsim simulation and download configuration based on EP2C5Q208C binary frequency
(系统自动生成,下载前可以参看下载内容)

下载文件列表

clk/
clk/clk.asm.rpt
clk/clk.done
clk/clk.eda.rpt
clk/clk.fit.rpt
clk/clk.fit.smsg
clk/clk.fit.summary
clk/clk.flow.rpt
clk/clk.map.rpt
clk/clk.map.summary
clk/clk.pin
clk/clk.pof
clk/clk.qpf
clk/clk.qsf
clk/clk.sof
clk/clk.sta.rpt
clk/clk.sta.summary
clk/clk.v
clk/clk.v.bak
clk/clk_nativelink_simulation.rpt
clk/db/
clk/db/clk.(0).cnf.cdb
clk/db/clk.(0).cnf.hdb
clk/db/clk.amm.cdb
clk/db/clk.asm.qmsg
clk/db/clk.asm.rdb
clk/db/clk.asm_labs.ddb
clk/db/clk.cbx.xml
clk/db/clk.cmp.bpm
clk/db/clk.cmp.cdb
clk/db/clk.cmp.hdb
clk/db/clk.cmp.kpt
clk/db/clk.cmp.logdb
clk/db/clk.cmp.rdb
clk/db/clk.cmp0.ddb
clk/db/clk.cmp1.ddb
clk/db/clk.cmp2.ddb
clk/db/clk.cmp_merge.kpt
clk/db/clk.db_info
clk/db/clk.eda.qmsg
clk/db/clk.fit.qmsg
clk/db/clk.hier_info
clk/db/clk.hif
clk/db/clk.idb.cdb
clk/db/clk.lpc.html
clk/db/clk.lpc.rdb
clk/db/clk.lpc.txt
clk/db/clk.map.bpm
clk/db/clk.map.cdb
clk/db/clk.map.hdb
clk/db/clk.map.kpt
clk/db/clk.map.logdb
clk/db/clk.map.qmsg
clk/db/clk.map_bb.cdb
clk/db/clk.map_bb.hdb
clk/db/clk.map_bb.logdb
clk/db/clk.pre_map.cdb
clk/db/clk.pre_map.hdb
clk/db/clk.rtlv.hdb
clk/db/clk.rtlv_sg.cdb
clk/db/clk.rtlv_sg_swap.cdb
clk/db/clk.sgdiff.cdb
clk/db/clk.sgdiff.hdb
clk/db/clk.sld_design_entry.sci
clk/db/clk.sld_design_entry_dsc.sci
clk/db/clk.smart_action.txt
clk/db/clk.sta.qmsg
clk/db/clk.sta.rdb
clk/db/clk.sta_cmp.8_slow.tdb
clk/db/clk.syn_hier_info
clk/db/clk.tis_db_list.ddb
clk/db/clk.tmw_info
clk/db/logic_util_heursitic.dat
clk/db/prev_cmp_clk.qmsg
clk/incremental_db/
clk/incremental_db/README
clk/incremental_db/compiled_partitions/
clk/incremental_db/compiled_partitions/clk.db_info
clk/incremental_db/compiled_partitions/clk.root_partition.cmp.cdb
clk/incremental_db/compiled_partitions/clk.root_partition.cmp.dfp
clk/incremental_db/compiled_partitions/clk.root_partition.cmp.hdb
clk/incremental_db/compiled_partitions/clk.root_partition.cmp.kpt
clk/incremental_db/compiled_partitions/clk.root_partition.cmp.logdb
clk/incremental_db/compiled_partitions/clk.root_partition.cmp.rcfdb
clk/incremental_db/compiled_partitions/clk.root_partition.map.cdb
clk/incremental_db/compiled_partitions/clk.root_partition.map.dpi
clk/incremental_db/compiled_partitions/clk.root_partition.map.hbdb.cdb
clk/incremental_db/compiled_partitions/clk.root_partition.map.hbdb.hb_info
clk/incremental_db/compiled_partitions/clk.root_partition.map.hbdb.hdb
clk/incremental_db/compiled_partitions/clk.root_partition.map.hbdb.sig
clk/incremental_db/compiled_partitions/clk.root_partition.map.hdb
clk/incremental_db/compiled_partitions/clk.root_partition.map.kpt
clk/simulation/
clk/simulation/modelsim/
clk/simulation/modelsim/clk.sft
clk/simulation/modelsim/clk.vo
clk/simulation/modelsim/clk.vt
clk/simulation/modelsim/clk.vt.bak
clk/simulation/modelsim/clk_fast.vo
clk/simulation/modelsim/clk_modelsim.xrf
clk/simulation/modelsim/clk_run_msim_rtl_verilog.do
clk/simulation/modelsim/clk_run_msim_rtl_verilog.do.bak
clk/simulation/modelsim/clk_run_msim_rtl_verilog.do.bak1
clk/simulation/modelsim/clk_v.sdo
clk/simulation/modelsim/clk_v_fast.sdo
clk/simulation/modelsim/modelsim.ini
clk/simulation/modelsim/msim_transcript
clk/simulation/modelsim/rtl_work/
clk/simulation/modelsim/rtl_work/_info
clk/simulation/modelsim/rtl_work/_temp/
clk/simulation/modelsim/rtl_work/_vmake
clk/simulation/modelsim/rtl_work/clk/
clk/simulation/modelsim/rtl_work/clk/_primary.dat
clk/simulation/modelsim/rtl_work/clk/_primary.dbs
clk/simulation/modelsim/rtl_work/clk/_primary.vhd
clk/simulation/modelsim/rtl_work/clk/verilog.prw
clk/simulation/modelsim/rtl_work/clk/verilog.psm
clk/simulation/modelsim/rtl_work/clk_vlg_tst/
clk/simulation/modelsim/rtl_work/clk_vlg_tst/_primary.dat
clk/simulation/modelsim/rtl_work/clk_vlg_tst/_primary.dbs
clk/simulation/modelsim/rtl_work/clk_vlg_tst/_primary.vhd
clk/simulation/modelsim/rtl_work/clk_vlg_tst/verilog.prw
clk/simulation/modelsim/rtl_work/clk_vlg_tst/verilog.psm
clk/simulation/modelsim/transcript
clk/simulation/modelsim/vsim.wlf

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