设计一个数据宽度8bit，深度是16的

同步FIFO(读写用同一时钟)，具有EMPTY、FULL输出标志。

要求FIFO的读写时钟频率为20MHz，

将1－16连续写入FIFO，写满后再将其读出来（读空为止）。

仿真上述逻辑的时序-Design a data width 8bit depth of 16 the synchronization FIFO (read and write with the same clock), EMPTY, FULL output flag. Requirements FIFO read and write clock frequency of 20MHz, to 1-16 consecutive write FIFO, and then filled it read out (read empty so far). Timing simulation above logic