文件名称:ZedBoard_OOB_Design
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- 上传时间:2012-11-16
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文件大小:7.73mb
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xilinx Zynq Digilent Zedboard上的可运行的Linux系统以及源码文件,有详细说明-xilinx Zynq Digilent Zedboard running Linux system as well as the source file, there is a detailed descr iption of
(系统自动生成,下载前可以参看下载内容)
下载文件列表
linux/.config
linux/devicetree_ramdisk.dts
sd_image/BOOT.BIN
sd_image/devicetree_ramdisk.dtb
sd_image/ramdisk8M.image.gz
sd_image/README
sd_image/zImage
sw/hw_platform/
sw/hw_platform/.project
sw/hw_platform/ps7_init.c
sw/hw_platform/ps7_init.h
sw/hw_platform/ps7_init.html
sw/hw_platform/ps7_init.tcl
sw/hw_platform/system.xml
sw/zynq_fsbl/
sw/zynq_fsbl/.cproject
sw/zynq_fsbl/.project
sw/zynq_fsbl/Debug/
sw/zynq_fsbl/Debug/makefile
sw/zynq_fsbl/Debug/objects.mk
sw/zynq_fsbl/Debug/sources.mk
sw/zynq_fsbl/Debug/src/
sw/zynq_fsbl/Debug/src/subdir.mk
sw/zynq_fsbl/src/
sw/zynq_fsbl/src/_exit.c
sw/zynq_fsbl/src/asm_vectors.s
sw/zynq_fsbl/src/boot.S
sw/zynq_fsbl/src/cpu_init.S
sw/zynq_fsbl/src/ddr_init.c
sw/zynq_fsbl/src/diskio.h
sw/zynq_fsbl/src/ff.c
sw/zynq_fsbl/src/ff.h
sw/zynq_fsbl/src/ffconf.h
sw/zynq_fsbl/src/fsbl.h
sw/zynq_fsbl/src/fsbl_handoff.S
sw/zynq_fsbl/src/image_mover.c
sw/zynq_fsbl/src/image_mover.h
sw/zynq_fsbl/src/integer.h
sw/zynq_fsbl/src/lscript.ld
sw/zynq_fsbl/src/main.c
sw/zynq_fsbl/src/mio.c
sw/zynq_fsbl/src/mio.h
sw/zynq_fsbl/src/mmc.c
sw/zynq_fsbl/src/nand.c
sw/zynq_fsbl/src/nand.h
sw/zynq_fsbl/src/nor.c
sw/zynq_fsbl/src/nor.h
sw/zynq_fsbl/src/outbyte.c
sw/zynq_fsbl/src/pcap.c
sw/zynq_fsbl/src/pcap.h
sw/zynq_fsbl/src/ps7_init.c
sw/zynq_fsbl/src/ps7_init.h
sw/zynq_fsbl/src/qspi.c
sw/zynq_fsbl/src/qspi.h
sw/zynq_fsbl/src/sd.c
sw/zynq_fsbl/src/sd.h
sw/zynq_fsbl/src/sd_hardware.h
sw/zynq_fsbl/src/smc.h
sw/zynq_fsbl/src/top_level.h
sw/zynq_fsbl/src/translation_table.s
sw/zynq_fsbl/src/uart.c
sw/zynq_fsbl/src/xbasic_types.c
sw/zynq_fsbl/src/xil_assert.h
sw/zynq_fsbl/src/xil_io.c
sw/zynq_fsbl/src/xil_io.h
sw/zynq_fsbl/src/xil_printf.c
sw/zynq_fsbl/src/xil_printf.h
sw/zynq_fsbl/src/xil_types.h
sw/zynq_fsbl/src/xil-crt0.S
sw/zynq_fsbl/src/xnandpss.c
sw/zynq_fsbl/src/xnandpss.h
sw/zynq_fsbl/src/xnandpss_bbm.c
sw/zynq_fsbl/src/xnandpss_bbm.h
sw/zynq_fsbl/src/xnandpss_hw.h
sw/zynq_fsbl/src/xnandpss_onfi.c
sw/zynq_fsbl/src/xnandpss_onfi.h
sw/zynq_fsbl/src/xparameters.h
sw/zynq_fsbl/src/xparameters_pss.h
sw/zynq_fsbl/src/xpseudo_asm.h
sw/zynq_fsbl/src/xpseudo_asm_gcc.h
sw/zynq_fsbl/src/xreg_cortexa9.h
sw/zynq_fsbl/src/xstatus.h
sw/zynq_fsbl/src/xuartpss.h
sw/zynq_fsbl/src/xuartpss_hw.c
sw/zynq_fsbl/src/xuartpss_hw.h
boot_image/system.bit
boot_image/u-boot.elf
boot_image/zynq_fsbl.elf
doc/README.txt
hw/xps_proj/
hw/xps_proj/data/
hw/xps_proj/data/ps7_constraints.ucf
hw/xps_proj/data/ps7_constraints.xdc
hw/xps_proj/data/ps7_system_prj.xml
hw/xps_proj/data/system.ucf
hw/xps_proj/pcores/
hw/xps_proj/pcores/axi_clkgen_v1_00_a/
hw/xps_proj/pcores/axi_clkgen_v1_00_a/data/
hw/xps_proj/pcores/axi_clkgen_v1_00_a/data/.svn/
hw/xps_proj/pcores/axi_clkgen_v1_00_a/data/.svn/entries
hw/xps_proj/pcores/axi_clkgen_v1_00_a/data/.svn/prop-base/
hw/xps_proj/pcores/axi_clkgen_v1_00_a/data/.svn/prop-base/_axi_clkgen_xst.prj.svn-base
hw/xps_proj/pcores/axi_clkgen_v1_00_a/data/.svn/prop-base/axi_clkgen_v2_1_0.mpd.svn-base
hw/xps_proj/pcores/axi_clkgen_v1_00_a/data/.svn/prop-base/axi_clkgen_v2_1_0.pao.svn-base
hw/xps_proj/pcores/axi_clkgen_v1_00_a/data/.svn/props/
hw/xps_proj/pcores/axi_clkgen_v1_00_a/data/.svn/text-base/
hw/xps_proj/pcores/axi_clkgen_v1_00_a/data/.svn/text-base/_axi_clkgen_xst.prj.svn-base
hw/xps_proj/pcores/axi_clkgen_v1_00_a/data/.svn/text-base/axi_clkgen_v2_1_0.mpd.svn-base
hw/xps_proj/pcores/axi_clkgen_v1_00_a/data/.svn/text-base/axi_clkgen_v2_1_0.pao.svn-base
hw/xps_proj/pcores/axi_clkgen_v1_00_a/data/.svn/tmp/
hw/xps_proj/pcores/axi_clkgen_v1_00_a/data/.svn/tmp/prop-base/
hw/xps_proj/pcores/axi_clkgen_v1_00_a/data/.svn/tmp/props/
hw/xps_proj/pcores/axi_clkgen_v1_00_a/data/.svn/tmp/text-base/
hw/xps_proj/pcores/axi_clkgen_v1_00_a/data/_axi_clkgen_xst.prj
hw/xps_proj/pcores/axi_clkgen_v1_00_a/data/axi_clkgen_v2_1_0.mpd
hw/xps_proj/pcores/axi_clkgen_v1_00_a/data/axi_clkgen_v2_1_0.pao
hw/xps_proj/pcores/axi_clkgen_v1_00_a/hdl/
hw/xps_proj/pcores/axi_clkgen_v1_00_a/hdl/verilog/
hw/xps_proj/pcores/axi_clkgen_v1_00_a/hdl/verilog/.svn/
hw/xps_proj/pcores/axi_clkgen_v1_00_a/hdl/verilog/.svn/entries
hw/xps_proj/pcores/axi_clkgen_v1_00_a/hdl/verilog/.svn/prop-base/
hw/xps_proj/pcores/axi_clkgen_v1_00_a/hdl/verilog/.svn/prop-base/cf_clkgen.v.svn-base
hw/xps_proj/pcores/axi_clkgen_v1_00_a/hdl/verilog/.svn/prop-base/user_logic.v.svn-base
hw/xps_proj/pcores/axi_clkgen_v1_00_a/hdl/verilog/.svn/props/
hw/xps_proj/pcores/axi_clkgen_v1_00_a/hdl/verilog/.svn/text-base/
hw/xps_proj/pcores/axi_clkgen_v1_00_a/hdl/verilog/.svn/text-base/cf_clkgen.v.svn-base
hw/xps_proj/pcores/axi_clkgen_v1_00_a/hdl/verilog/.svn/text-base/user_logic.v.svn-base
hw/xps_proj/pcores/axi_clkgen_v1_00_a/hdl/verilog/.svn/tmp/
hw/xps_proj/pcores/axi_clkgen_v1_00_a/hdl/verilog/.svn/tmp/prop-base/
hw/xps_proj/pcores/axi_clkgen_v1_00_a/hdl/verilog/.svn/tmp/props/
hw/xps_proj/pcores/axi_clkgen_v1_00_a/hdl/verilog/.svn/tmp/text-base/
hw/xps_proj/pcores/axi_clkgen_v1_00_a/hdl/verilog/cf_clkgen.v
hw/xps_proj/pcores/axi_clkgen_v1_00_a/hdl/verilog/user_logic.v
hw/xps_proj/pcores/axi_clkgen_v1_00_a/hdl/vhdl/
hw/xps_proj/pcores/axi_clkgen_v1_00_a/hdl/vhdl/.svn/
hw/xps_proj/pcores/ax
linux/devicetree_ramdisk.dts
sd_image/BOOT.BIN
sd_image/devicetree_ramdisk.dtb
sd_image/ramdisk8M.image.gz
sd_image/README
sd_image/zImage
sw/hw_platform/
sw/hw_platform/.project
sw/hw_platform/ps7_init.c
sw/hw_platform/ps7_init.h
sw/hw_platform/ps7_init.html
sw/hw_platform/ps7_init.tcl
sw/hw_platform/system.xml
sw/zynq_fsbl/
sw/zynq_fsbl/.cproject
sw/zynq_fsbl/.project
sw/zynq_fsbl/Debug/
sw/zynq_fsbl/Debug/makefile
sw/zynq_fsbl/Debug/objects.mk
sw/zynq_fsbl/Debug/sources.mk
sw/zynq_fsbl/Debug/src/
sw/zynq_fsbl/Debug/src/subdir.mk
sw/zynq_fsbl/src/
sw/zynq_fsbl/src/_exit.c
sw/zynq_fsbl/src/asm_vectors.s
sw/zynq_fsbl/src/boot.S
sw/zynq_fsbl/src/cpu_init.S
sw/zynq_fsbl/src/ddr_init.c
sw/zynq_fsbl/src/diskio.h
sw/zynq_fsbl/src/ff.c
sw/zynq_fsbl/src/ff.h
sw/zynq_fsbl/src/ffconf.h
sw/zynq_fsbl/src/fsbl.h
sw/zynq_fsbl/src/fsbl_handoff.S
sw/zynq_fsbl/src/image_mover.c
sw/zynq_fsbl/src/image_mover.h
sw/zynq_fsbl/src/integer.h
sw/zynq_fsbl/src/lscript.ld
sw/zynq_fsbl/src/main.c
sw/zynq_fsbl/src/mio.c
sw/zynq_fsbl/src/mio.h
sw/zynq_fsbl/src/mmc.c
sw/zynq_fsbl/src/nand.c
sw/zynq_fsbl/src/nand.h
sw/zynq_fsbl/src/nor.c
sw/zynq_fsbl/src/nor.h
sw/zynq_fsbl/src/outbyte.c
sw/zynq_fsbl/src/pcap.c
sw/zynq_fsbl/src/pcap.h
sw/zynq_fsbl/src/ps7_init.c
sw/zynq_fsbl/src/ps7_init.h
sw/zynq_fsbl/src/qspi.c
sw/zynq_fsbl/src/qspi.h
sw/zynq_fsbl/src/sd.c
sw/zynq_fsbl/src/sd.h
sw/zynq_fsbl/src/sd_hardware.h
sw/zynq_fsbl/src/smc.h
sw/zynq_fsbl/src/top_level.h
sw/zynq_fsbl/src/translation_table.s
sw/zynq_fsbl/src/uart.c
sw/zynq_fsbl/src/xbasic_types.c
sw/zynq_fsbl/src/xil_assert.h
sw/zynq_fsbl/src/xil_io.c
sw/zynq_fsbl/src/xil_io.h
sw/zynq_fsbl/src/xil_printf.c
sw/zynq_fsbl/src/xil_printf.h
sw/zynq_fsbl/src/xil_types.h
sw/zynq_fsbl/src/xil-crt0.S
sw/zynq_fsbl/src/xnandpss.c
sw/zynq_fsbl/src/xnandpss.h
sw/zynq_fsbl/src/xnandpss_bbm.c
sw/zynq_fsbl/src/xnandpss_bbm.h
sw/zynq_fsbl/src/xnandpss_hw.h
sw/zynq_fsbl/src/xnandpss_onfi.c
sw/zynq_fsbl/src/xnandpss_onfi.h
sw/zynq_fsbl/src/xparameters.h
sw/zynq_fsbl/src/xparameters_pss.h
sw/zynq_fsbl/src/xpseudo_asm.h
sw/zynq_fsbl/src/xpseudo_asm_gcc.h
sw/zynq_fsbl/src/xreg_cortexa9.h
sw/zynq_fsbl/src/xstatus.h
sw/zynq_fsbl/src/xuartpss.h
sw/zynq_fsbl/src/xuartpss_hw.c
sw/zynq_fsbl/src/xuartpss_hw.h
boot_image/system.bit
boot_image/u-boot.elf
boot_image/zynq_fsbl.elf
doc/README.txt
hw/xps_proj/
hw/xps_proj/data/
hw/xps_proj/data/ps7_constraints.ucf
hw/xps_proj/data/ps7_constraints.xdc
hw/xps_proj/data/ps7_system_prj.xml
hw/xps_proj/data/system.ucf
hw/xps_proj/pcores/
hw/xps_proj/pcores/axi_clkgen_v1_00_a/
hw/xps_proj/pcores/axi_clkgen_v1_00_a/data/
hw/xps_proj/pcores/axi_clkgen_v1_00_a/data/.svn/
hw/xps_proj/pcores/axi_clkgen_v1_00_a/data/.svn/entries
hw/xps_proj/pcores/axi_clkgen_v1_00_a/data/.svn/prop-base/
hw/xps_proj/pcores/axi_clkgen_v1_00_a/data/.svn/prop-base/_axi_clkgen_xst.prj.svn-base
hw/xps_proj/pcores/axi_clkgen_v1_00_a/data/.svn/prop-base/axi_clkgen_v2_1_0.mpd.svn-base
hw/xps_proj/pcores/axi_clkgen_v1_00_a/data/.svn/prop-base/axi_clkgen_v2_1_0.pao.svn-base
hw/xps_proj/pcores/axi_clkgen_v1_00_a/data/.svn/props/
hw/xps_proj/pcores/axi_clkgen_v1_00_a/data/.svn/text-base/
hw/xps_proj/pcores/axi_clkgen_v1_00_a/data/.svn/text-base/_axi_clkgen_xst.prj.svn-base
hw/xps_proj/pcores/axi_clkgen_v1_00_a/data/.svn/text-base/axi_clkgen_v2_1_0.mpd.svn-base
hw/xps_proj/pcores/axi_clkgen_v1_00_a/data/.svn/text-base/axi_clkgen_v2_1_0.pao.svn-base
hw/xps_proj/pcores/axi_clkgen_v1_00_a/data/.svn/tmp/
hw/xps_proj/pcores/axi_clkgen_v1_00_a/data/.svn/tmp/prop-base/
hw/xps_proj/pcores/axi_clkgen_v1_00_a/data/.svn/tmp/props/
hw/xps_proj/pcores/axi_clkgen_v1_00_a/data/.svn/tmp/text-base/
hw/xps_proj/pcores/axi_clkgen_v1_00_a/data/_axi_clkgen_xst.prj
hw/xps_proj/pcores/axi_clkgen_v1_00_a/data/axi_clkgen_v2_1_0.mpd
hw/xps_proj/pcores/axi_clkgen_v1_00_a/data/axi_clkgen_v2_1_0.pao
hw/xps_proj/pcores/axi_clkgen_v1_00_a/hdl/
hw/xps_proj/pcores/axi_clkgen_v1_00_a/hdl/verilog/
hw/xps_proj/pcores/axi_clkgen_v1_00_a/hdl/verilog/.svn/
hw/xps_proj/pcores/axi_clkgen_v1_00_a/hdl/verilog/.svn/entries
hw/xps_proj/pcores/axi_clkgen_v1_00_a/hdl/verilog/.svn/prop-base/
hw/xps_proj/pcores/axi_clkgen_v1_00_a/hdl/verilog/.svn/prop-base/cf_clkgen.v.svn-base
hw/xps_proj/pcores/axi_clkgen_v1_00_a/hdl/verilog/.svn/prop-base/user_logic.v.svn-base
hw/xps_proj/pcores/axi_clkgen_v1_00_a/hdl/verilog/.svn/props/
hw/xps_proj/pcores/axi_clkgen_v1_00_a/hdl/verilog/.svn/text-base/
hw/xps_proj/pcores/axi_clkgen_v1_00_a/hdl/verilog/.svn/text-base/cf_clkgen.v.svn-base
hw/xps_proj/pcores/axi_clkgen_v1_00_a/hdl/verilog/.svn/text-base/user_logic.v.svn-base
hw/xps_proj/pcores/axi_clkgen_v1_00_a/hdl/verilog/.svn/tmp/
hw/xps_proj/pcores/axi_clkgen_v1_00_a/hdl/verilog/.svn/tmp/prop-base/
hw/xps_proj/pcores/axi_clkgen_v1_00_a/hdl/verilog/.svn/tmp/props/
hw/xps_proj/pcores/axi_clkgen_v1_00_a/hdl/verilog/.svn/tmp/text-base/
hw/xps_proj/pcores/axi_clkgen_v1_00_a/hdl/verilog/cf_clkgen.v
hw/xps_proj/pcores/axi_clkgen_v1_00_a/hdl/verilog/user_logic.v
hw/xps_proj/pcores/axi_clkgen_v1_00_a/hdl/vhdl/
hw/xps_proj/pcores/axi_clkgen_v1_00_a/hdl/vhdl/.svn/
hw/xps_proj/pcores/ax
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