文件名称:dual ram
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- 上传时间:2012-11-28
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文件大小:1.33mb
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此文件是FPGA工程文件,包含了dualram的设计代码和testbench代码,使用了verilog hdl编写,仿真结果符合设计要求。
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压缩包 : dual ram.rar 列表 dual ram/db/altsyncram_3ld1.tdf dual ram/db/Dual.(0).cnf.cdb dual ram/db/Dual.(0).cnf.hdb dual ram/db/Dual.(1).cnf.cdb dual ram/db/Dual.(1).cnf.hdb dual ram/db/Dual.(2).cnf.cdb dual ram/db/Dual.(2).cnf.hdb dual ram/db/Dual.(3).cnf.cdb dual ram/db/Dual.(3).cnf.hdb dual ram/db/Dual.(4).cnf.cdb dual ram/db/Dual.(4).cnf.hdb dual ram/db/Dual.(5).cnf.cdb dual ram/db/Dual.(5).cnf.hdb dual ram/db/Dual.(6).cnf.cdb dual ram/db/Dual.(6).cnf.hdb dual ram/db/Dual.ace_cmp.bpm dual ram/db/Dual.ace_cmp.cdb dual ram/db/Dual.ace_cmp.hdb dual ram/db/Dual.ae.hdb dual ram/db/Dual.amm.cdb dual ram/db/Dual.asm.qmsg dual ram/db/Dual.asm.rdb dual ram/db/Dual.asm_labs.ddb dual ram/db/Dual.cbx.xml dual ram/db/Dual.cmp.bpm dual ram/db/Dual.cmp.cdb dual ram/db/Dual.cmp.hdb dual ram/db/Dual.cmp.kpt dual ram/db/Dual.cmp.logdb dual ram/db/Dual.cmp.rdb dual ram/db/Dual.cmp_merge.kpt dual ram/db/Dual.cuda_io_sim_cache.45um_ff_1200mv_0c_fast.hsd dual ram/db/Dual.cuda_io_sim_cache.45um_ii_1200mv_85c_slow.hsd dual ram/db/Dual.db_info dual ram/db/Dual.eco.cdb dual ram/db/Dual.eda.qmsg dual ram/db/Dual.fit.qmsg dual ram/db/Dual.hier_info dual ram/db/Dual.hif dual ram/db/Dual.idb.cdb dual ram/db/Dual.lpc.html dual ram/db/Dual.lpc.rdb dual ram/db/Dual.lpc.txt dual ram/db/Dual.map.bpm dual ram/db/Dual.map.cdb dual ram/db/Dual.map.hdb dual ram/db/Dual.map.kpt dual ram/db/Dual.map.logdb dual ram/db/Dual.map.qmsg dual ram/db/Dual.map_bb.cdb dual ram/db/Dual.map_bb.hdb dual ram/db/Dual.map_bb.logdb dual ram/db/Dual.pre_map.cdb dual ram/db/Dual.pre_map.hdb dual ram/db/Dual.rpp.qmsg dual ram/db/Dual.rtlv.hdb dual ram/db/Dual.rtlv_sg.cdb dual ram/db/Dual.rtlv_sg_swap.cdb dual ram/db/Dual.sgate.rvd dual ram/db/Dual.sgate_sm.rvd dual ram/db/Dual.sgdiff.cdb dual ram/db/Dual.sgdiff.hdb dual ram/db/Dual.sld_design_entry.sci dual ram/db/Dual.sld_design_entry_dsc.sci dual ram/db/Dual.smart_action.txt dual ram/db/Dual.sta.qmsg dual ram/db/Dual.sta.rdb dual ram/db/Dual.sta_cmp.7_slow_1200mv_85c.tdb dual ram/db/Dual.syn_hier_info dual ram/db/Dual.tiscmp.fast_1200mv_0c.ddb dual ram/db/Dual.tiscmp.slow_1200mv_0c.ddb dual ram/db/Dual.tiscmp.slow_1200mv_85c.ddb dual ram/db/Dual.tis_db_list.ddb dual ram/db/Dual.tmw_info dual ram/db/logic_util_heursitic.dat dual ram/db/prev_cmp_Dual.qmsg dual ram/Dual.asm.rpt dual ram/Dual.done dual ram/Dual.eda.rpt dual ram/Dual.fit.rpt dual ram/Dual.fit.smsg dual ram/Dual.fit.summary dual ram/Dual.flow.rpt dual ram/Dual.map.rpt dual ram/Dual.map.summary dual ram/Dual.pin dual ram/Dual.qpf dual ram/Dual.qsf dual ram/Dual.sof dual ram/Dual.sta.rpt dual ram/Dual.sta.summary dual ram/Dual.tis_db_list.ddb dual ram/Dual.v dual ram/Dual.v.bak dual ram/Dual_nativelink_simulation.rpt dual ram/incremental_db/compiled_partitions/Dual.db_info dual ram/incremental_db/compiled_partitions/Dual.root_partition.cmp.cdb dual ram/incremental_db/compiled_partitions/Dual.root_partition.cmp.dfp dual ram/incremental_db/compiled_partitions/Dual.root_partition.cmp.hdb dual ram/incremental_db/compiled_partitions/Dual.root_partition.cmp.kpt dual ram/incremental_db/compiled_partitions/Dual.root_partition.cmp.logdb dual ram/incremental_db/compiled_partitions/Dual.root_partition.cmp.rcfdb dual ram/incremental_db/compiled_partitions/Dual.root_partition.map.cdb dual ram/incremental_db/compiled_partitions/Dual.root_partition.map.dpi dual ram/incremental_db/compiled_partitions/Dual.root_partition.map.hbdb.cdb dual ram/incremental_db/compiled_partitions/Dual.root_partition.map.hbdb.hb_info dual ram/incremental_db/compiled_partitions/Dual.root_partition.map.hbdb.hdb dual ram/incremental_db/compiled_partitions/Dual.root_partition.map.hbdb.sig dual ram/incremental_db/compiled_partitions/Dual.root_partition.map.hdb dual ram/incremental_db/compiled_partitions/Dual.root_partition.map.kpt dual ram/incremental_db/README dual ram/simulation/modelsim/Dual.sft dual ram/simulation/modelsim/Dual.vo dual ram/simulation/modelsim/Dual.vt dual ram/simulation/modelsim/Dual.vt.bak dual ram/simulation/modelsim/Dual_7_1200mv_0c_slow.vo dual ram/simulation/modelsim/Dual_7_1200mv_0c_v_slow.sdo dual ram/simulation/modelsim/Dual_7_1200mv_85c_slow.vo dual ram/simulation/modelsim/Dual_7_1200mv_85c_v_slow.sdo dual ram/simulation/modelsim/Dual_7_1200mv_85c_v_slow.sdo_typ.csd dual ram/simulation/modelsim/Dual_min_1200mv_0c_fast.vo dual ram/simulation/modelsim/Dual_min_1200mv_0c_v_fast.sdo dual ram/simulation/modelsim/Dual_modelsim.xrf dual ram/simulation/modelsim/Dual_run_msim_gate_verilog.do dual ram/simulation/modelsim/Dual_run_msim_rtl_verilog.do dual ram/simulation/modelsim/Dual_run_msim_rtl_verilog.do.bak dual ram/simulation/modelsim/Dual_run_msim_rtl_verilog.do.bak1 dual ram/simulation/modelsim/Dual_run_msim_rtl_verilog.do.bak10 dual ram/simulation/modelsim/Dual_run_msim_rtl_verilog.do.bak11 dual ram/simulation/modelsim/Dual_run_msim_rtl_verilog.do.bak2 dual ram/simulation/modelsim/Dual_run_msim_rtl_verilog.do.bak3 dual ram/simulation/modelsim/Dual_run_msim_rtl_verilog.do.bak4 dual ram/simulation/modelsim/Dual_run_msim_rtl_verilog.do.bak5 dual ram/simulation/modelsim/Dual_run_msim_rtl_verilog.do.bak6 dual ram/si
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