文件名称:ARM-Verilog-HDL-IP-CORE
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- 上传时间:2012-12-06
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文件大小:73.21kb
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ARM处理器的IP核,用verilog编写的,对处理器和相关的CPU架构知识有很大帮助。-ARM processor IP core, written in verilog processor and CPU architecture knowledge.
(系统自动生成,下载前可以参看下载内容)
下载文件列表
ARM Verilog HDL IP CORE(vhdl)/
ARM Verilog HDL IP CORE(vhdl)/ABORTGenerator.vhd
ARM Verilog HDL IP CORE(vhdl)/ABusMultiplexer.vhd
ARM Verilog HDL IP CORE(vhdl)/AddressMux_Incrementer.vhd
ARM Verilog HDL IP CORE(vhdl)/AdrCtrlReg.vhd
ARM Verilog HDL IP CORE(vhdl)/ALU.vhd
ARM Verilog HDL IP CORE(vhdl)/ALUTesterSim.vhd
ARM Verilog HDL IP CORE(vhdl)/ARM7TDMIS_Top.vhd
ARM Verilog HDL IP CORE(vhdl)/ARMALUTestTop.vhd
ARM Verilog HDL IP CORE(vhdl)/ARMCoreSimTop.vhd
ARM Verilog HDL IP CORE(vhdl)/ARMMultiplierTestTop.vhd
ARM Verilog HDL IP CORE(vhdl)/ARMPackage.vhd
ARM Verilog HDL IP CORE(vhdl)/ARMShifterTestTop.vhd
ARM Verilog HDL IP CORE(vhdl)/ARMSimMemSubsystem.vhd
ARM Verilog HDL IP CORE(vhdl)/ARMSMSSPackage.vhd
ARM Verilog HDL IP CORE(vhdl)/BBusMultiplexer.vhd
ARM Verilog HDL IP CORE(vhdl)/BusMonitor.vhd
ARM Verilog HDL IP CORE(vhdl)/CLKENGenerator.vhd
ARM Verilog HDL IP CORE(vhdl)/ClockAndResetGenerator.vhd
ARM Verilog HDL IP CORE(vhdl)/ControlLogic.vhd
ARM Verilog HDL IP CORE(vhdl)/CycleCounter.vhd
ARM Verilog HDL IP CORE(vhdl)/DataMux.vhd
ARM Verilog HDL IP CORE(vhdl)/DataOutMux.vhd
ARM Verilog HDL IP CORE(vhdl)/Decoder.vhd
ARM Verilog HDL IP CORE(vhdl)/IPDR.vhd
ARM Verilog HDL IP CORE(vhdl)/LSAdrGen.vhd
ARM Verilog HDL IP CORE(vhdl)/MemoryRemapper.vhd
ARM Verilog HDL IP CORE(vhdl)/MSSCompPackage.vhd
ARM Verilog HDL IP CORE(vhdl)/Mul32x8Comb.vhd
ARM Verilog HDL IP CORE(vhdl)/MulCtrlAndRegs.vhd
ARM Verilog HDL IP CORE(vhdl)/Multiplier.vhd
ARM Verilog HDL IP CORE(vhdl)/MultiplierTestAdder.vhd
ARM Verilog HDL IP CORE(vhdl)/MultiplierTesterSim.vhd
ARM Verilog HDL IP CORE(vhdl)/PSR.vhd
ARM Verilog HDL IP CORE(vhdl)/RAM32B.vhd
ARM Verilog HDL IP CORE(vhdl)/RegFile.vhd
ARM Verilog HDL IP CORE(vhdl)/ResltBitMask.vhd
ARM Verilog HDL IP CORE(vhdl)/ROMS19FR.vhd
ARM Verilog HDL IP CORE(vhdl)/S19FRPackage.vhd
ARM Verilog HDL IP CORE(vhdl)/ShiftAmountReg.vhd
ARM Verilog HDL IP CORE(vhdl)/Shifter.vhd
ARM Verilog HDL IP CORE(vhdl)/ShifterTestbench.vhd
ARM Verilog HDL IP CORE(vhdl)/ShifterTesterSim.vhd
ARM Verilog HDL IP CORE(vhdl)/ThumbDecoder.vhd
ARM Verilog HDL IP CORE(vhdl)/使用说明请参看右侧注释===〉〉.txt
ARM Verilog HDL IP CORE(vhdl)/ABORTGenerator.vhd
ARM Verilog HDL IP CORE(vhdl)/ABusMultiplexer.vhd
ARM Verilog HDL IP CORE(vhdl)/AddressMux_Incrementer.vhd
ARM Verilog HDL IP CORE(vhdl)/AdrCtrlReg.vhd
ARM Verilog HDL IP CORE(vhdl)/ALU.vhd
ARM Verilog HDL IP CORE(vhdl)/ALUTesterSim.vhd
ARM Verilog HDL IP CORE(vhdl)/ARM7TDMIS_Top.vhd
ARM Verilog HDL IP CORE(vhdl)/ARMALUTestTop.vhd
ARM Verilog HDL IP CORE(vhdl)/ARMCoreSimTop.vhd
ARM Verilog HDL IP CORE(vhdl)/ARMMultiplierTestTop.vhd
ARM Verilog HDL IP CORE(vhdl)/ARMPackage.vhd
ARM Verilog HDL IP CORE(vhdl)/ARMShifterTestTop.vhd
ARM Verilog HDL IP CORE(vhdl)/ARMSimMemSubsystem.vhd
ARM Verilog HDL IP CORE(vhdl)/ARMSMSSPackage.vhd
ARM Verilog HDL IP CORE(vhdl)/BBusMultiplexer.vhd
ARM Verilog HDL IP CORE(vhdl)/BusMonitor.vhd
ARM Verilog HDL IP CORE(vhdl)/CLKENGenerator.vhd
ARM Verilog HDL IP CORE(vhdl)/ClockAndResetGenerator.vhd
ARM Verilog HDL IP CORE(vhdl)/ControlLogic.vhd
ARM Verilog HDL IP CORE(vhdl)/CycleCounter.vhd
ARM Verilog HDL IP CORE(vhdl)/DataMux.vhd
ARM Verilog HDL IP CORE(vhdl)/DataOutMux.vhd
ARM Verilog HDL IP CORE(vhdl)/Decoder.vhd
ARM Verilog HDL IP CORE(vhdl)/IPDR.vhd
ARM Verilog HDL IP CORE(vhdl)/LSAdrGen.vhd
ARM Verilog HDL IP CORE(vhdl)/MemoryRemapper.vhd
ARM Verilog HDL IP CORE(vhdl)/MSSCompPackage.vhd
ARM Verilog HDL IP CORE(vhdl)/Mul32x8Comb.vhd
ARM Verilog HDL IP CORE(vhdl)/MulCtrlAndRegs.vhd
ARM Verilog HDL IP CORE(vhdl)/Multiplier.vhd
ARM Verilog HDL IP CORE(vhdl)/MultiplierTestAdder.vhd
ARM Verilog HDL IP CORE(vhdl)/MultiplierTesterSim.vhd
ARM Verilog HDL IP CORE(vhdl)/PSR.vhd
ARM Verilog HDL IP CORE(vhdl)/RAM32B.vhd
ARM Verilog HDL IP CORE(vhdl)/RegFile.vhd
ARM Verilog HDL IP CORE(vhdl)/ResltBitMask.vhd
ARM Verilog HDL IP CORE(vhdl)/ROMS19FR.vhd
ARM Verilog HDL IP CORE(vhdl)/S19FRPackage.vhd
ARM Verilog HDL IP CORE(vhdl)/ShiftAmountReg.vhd
ARM Verilog HDL IP CORE(vhdl)/Shifter.vhd
ARM Verilog HDL IP CORE(vhdl)/ShifterTestbench.vhd
ARM Verilog HDL IP CORE(vhdl)/ShifterTesterSim.vhd
ARM Verilog HDL IP CORE(vhdl)/ThumbDecoder.vhd
ARM Verilog HDL IP CORE(vhdl)/使用说明请参看右侧注释===〉〉.txt
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