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文件名称:bps

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    2012-12-18
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    204.43kb
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FPGA的运用:基于verilog的任意波特率配置模块-The application of FPGA: Based on Verilog arbitrary baud rate configuration module


(系统自动生成,下载前可以参看下载内容)

下载文件列表

.sopc_builder/
.sopc_builder/filters.xml
.sopc_builder/preferences.xml
bps.asm.rpt
bps.done
bps.dpf
bps.eda.rpt
bps.fit.rpt
bps.fit.smsg
bps.fit.summary
bps.flow.rpt
bps.map.rpt
bps.map.summary
bps.pin
bps.pof
bps.qpf
bps.qsf
bps.qws
bps.sim.rpt
bps.sof
bps.sta.rpt
bps.sta.summary
bps.tan.rpt
bps.tan.summary
bps.v
bps.v.bak
bps.vwf
bps_assignment_defaults.qdf
bps_nativelink_simulation.rpt
db/
db/bps.(0).cnf.cdb
db/bps.(0).cnf.hdb
db/bps.cbx.xml
db/bps.cmp.rdb
db/bps.db_info
db/bps.eco.cdb
db/bps.hier_info
db/bps.hif
db/bps.lpc.html
db/bps.lpc.rdb
db/bps.lpc.txt
db/bps.map.ecobp
db/bps.map.kpt
db/bps.map.qmsg
db/bps.map_bb.cdb
db/bps.map_bb.hdb
db/bps.map_bb.logdb
db/bps.pre_map.cdb
db/bps.pre_map.hdb
db/bps.rtlv.hdb
db/bps.rtlv_sg.cdb
db/bps.rtlv_sg_swap.cdb
db/bps.sgdiff.cdb
db/bps.sgdiff.hdb
db/bps.sim.cvwf
db/bps.sld_design_entry.sci
db/bps.sld_design_entry_dsc.sci
db/bps.syn_hier_info
db/bps.tis_db_list.ddb
db/logic_util_heursitic.dat
db/prev_cmp_bps.asm.qmsg
db/prev_cmp_bps.eda.qmsg
db/prev_cmp_bps.fit.qmsg
db/prev_cmp_bps.map.qmsg
db/prev_cmp_bps.qmsg
db/prev_cmp_bps.sim.qmsg
db/prev_cmp_bps.tan.qmsg
db/wed.wsf
incremental_db/
incremental_db/compiled_partitions/
incremental_db/compiled_partitions/bps.root_partition.cmp.cdb
incremental_db/compiled_partitions/bps.root_partition.cmp.dfp
incremental_db/compiled_partitions/bps.root_partition.cmp.hdb
incremental_db/compiled_partitions/bps.root_partition.cmp.kpt
incremental_db/compiled_partitions/bps.root_partition.cmp.logdb
incremental_db/compiled_partitions/bps.root_partition.cmp.rcfdb
incremental_db/compiled_partitions/bps.root_partition.cmp.re.rcfdb
incremental_db/compiled_partitions/bps.root_partition.map.atm
incremental_db/compiled_partitions/bps.root_partition.map.cdb
incremental_db/compiled_partitions/bps.root_partition.map.dpi
incremental_db/compiled_partitions/bps.root_partition.map.hdb
incremental_db/compiled_partitions/bps.root_partition.map.hdbx
incremental_db/compiled_partitions/bps.root_partition.map.kpt
incremental_db/README
lcd_11.bdf
serv_req_info.txt
simulation/
simulation/modelsim/
simulation/modelsim/bps.sft
simulation/modelsim/bps.vo
simulation/modelsim/bps.vt
simulation/modelsim/bps.vt.bak
simulation/modelsim/bps_modelsim.xrf
simulation/modelsim/bps_run_msim_rtl_verilog.do
simulation/modelsim/bps_run_msim_rtl_verilog.do.bak
simulation/modelsim/bps_run_msim_rtl_verilog.do.bak1
simulation/modelsim/bps_run_msim_rtl_verilog.do.bak10
simulation/modelsim/bps_run_msim_rtl_verilog.do.bak11
simulation/modelsim/bps_run_msim_rtl_verilog.do.bak2
simulation/modelsim/bps_run_msim_rtl_verilog.do.bak3
simulation/modelsim/bps_run_msim_rtl_verilog.do.bak4
simulation/modelsim/bps_run_msim_rtl_verilog.do.bak5
simulation/modelsim/bps_run_msim_rtl_verilog.do.bak6
simulation/modelsim/bps_run_msim_rtl_verilog.do.bak7
simulation/modelsim/bps_run_msim_rtl_verilog.do.bak8
simulation/modelsim/bps_run_msim_rtl_verilog.do.bak9
simulation/modelsim/bps_v.sdo
simulation/modelsim/modelsim.ini
simulation/modelsim/msim_transcript
simulation/modelsim/rtl_work/
simulation/modelsim/rtl_work/bps/
simulation/modelsim/rtl_work/bps/verilog.psm
simulation/modelsim/rtl_work/bps/_primary.dat
simulation/modelsim/rtl_work/bps/_primary.dbs
simulation/modelsim/rtl_work/bps/_primary.vhd
simulation/modelsim/rtl_work/bps_vlg_tst/
simulation/modelsim/rtl_work/bps_vlg_tst/verilog.psm
simulation/modelsim/rtl_work/bps_vlg_tst/_primary.dat
simulation/modelsim/rtl_work/bps_vlg_tst/_primary.dbs
simulation/modelsim/rtl_work/bps_vlg_tst/_primary.vhd
simulation/modelsim/rtl_work/_info
simulation/modelsim/rtl_work/_temp/
simulation/modelsim/rtl_work/_vmake
simulation/modelsim/vsim.wlf
sopc_builder_log.txt
undo_redo.txt

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