文件名称:memorynios
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- 上传时间:2012-12-31
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文件大小:664.36kb
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已下载:0次
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Altera Fpga 的存储器应用。主要以SDRAM、FLASH、SRAM存储器为主的FPGA存储器系统的扩充与应用。-Altera Fpga memory applications. Main the FPGA memory system based SDRAM, FLASH, SRAM memory expansion.
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下载文件列表
memorynios/delay_reset_block.bdf
memorynios/delay_reset_block.bsf
memorynios/memorynios.bsf
memorynios/memory_top.bdf
memorynios/sd_pll.bsf
memorynios/software/flash_test_simple_0/flash_test_simple.c
memorynios/software/hello_led_0/hello_led.c
memorynios/SRAM/cb_generator.pl
memorynios/SRAM/class.ptf
memorynios/SRAM/hdl/SRAM.v
memorynios/SRAM/hdl/SRAM_hw.tcl
memorynios/SRAM/sram_16bit_512k.v
memorynios/SRAM/SRAM_16Bit_512K_hw.tcl
memorynios/SRAM/版权声明.txt
memorynios/Verilog HDL Files/cpu_0.v
memorynios/Verilog HDL Files/cpu_0_jtag_debug_module_sysclk.v
memorynios/Verilog HDL Files/cpu_0_jtag_debug_module_tck.v
memorynios/Verilog HDL Files/cpu_0_jtag_debug_module_wrapper.v
memorynios/Verilog HDL Files/cpu_0_mult_cell.v
memorynios/Verilog HDL Files/cpu_0_oci_test_bench.v
memorynios/Verilog HDL Files/cpu_0_test_bench.v
memorynios/Verilog HDL Files/cpu_1.v
memorynios/Verilog HDL Files/cpu_1_jtag_debug_module_sysclk.v
memorynios/Verilog HDL Files/cpu_1_jtag_debug_module_tck.v
memorynios/Verilog HDL Files/cpu_1_jtag_debug_module_wrapper.v
memorynios/Verilog HDL Files/cpu_1_mult_cell.v
memorynios/Verilog HDL Files/cpu_1_oci_test_bench.v
memorynios/Verilog HDL Files/cpu_1_test_bench.v
memorynios/Verilog HDL Files/epcs_flash.v
memorynios/Verilog HDL Files/ext_sdram.v
memorynios/Verilog HDL Files/ext_sdram_test_component.v
memorynios/Verilog HDL Files/jtag_uart.v
memorynios/Verilog HDL Files/led_pio.v
memorynios/Verilog HDL Files/memorynios.v
memorynios/Verilog HDL Files/memorynios_inst.v
memorynios/Verilog HDL Files/reset_counter.v
memorynios/Verilog HDL Files/sd_pll.v
memorynios/Verilog HDL Files/sram_16bit_512k_0.v
memorynios/Verilog HDL Files/sysid.v
memorynios/software/flash_test_simple_0
memorynios/software/hello_led_0
memorynios/SRAM/hdl
memorynios/software
memorynios/SRAM
memorynios/Verilog HDL Files
memorynios
memorynios/delay_reset_block.bsf
memorynios/memorynios.bsf
memorynios/memory_top.bdf
memorynios/sd_pll.bsf
memorynios/software/flash_test_simple_0/flash_test_simple.c
memorynios/software/hello_led_0/hello_led.c
memorynios/SRAM/cb_generator.pl
memorynios/SRAM/class.ptf
memorynios/SRAM/hdl/SRAM.v
memorynios/SRAM/hdl/SRAM_hw.tcl
memorynios/SRAM/sram_16bit_512k.v
memorynios/SRAM/SRAM_16Bit_512K_hw.tcl
memorynios/SRAM/版权声明.txt
memorynios/Verilog HDL Files/cpu_0.v
memorynios/Verilog HDL Files/cpu_0_jtag_debug_module_sysclk.v
memorynios/Verilog HDL Files/cpu_0_jtag_debug_module_tck.v
memorynios/Verilog HDL Files/cpu_0_jtag_debug_module_wrapper.v
memorynios/Verilog HDL Files/cpu_0_mult_cell.v
memorynios/Verilog HDL Files/cpu_0_oci_test_bench.v
memorynios/Verilog HDL Files/cpu_0_test_bench.v
memorynios/Verilog HDL Files/cpu_1.v
memorynios/Verilog HDL Files/cpu_1_jtag_debug_module_sysclk.v
memorynios/Verilog HDL Files/cpu_1_jtag_debug_module_tck.v
memorynios/Verilog HDL Files/cpu_1_jtag_debug_module_wrapper.v
memorynios/Verilog HDL Files/cpu_1_mult_cell.v
memorynios/Verilog HDL Files/cpu_1_oci_test_bench.v
memorynios/Verilog HDL Files/cpu_1_test_bench.v
memorynios/Verilog HDL Files/epcs_flash.v
memorynios/Verilog HDL Files/ext_sdram.v
memorynios/Verilog HDL Files/ext_sdram_test_component.v
memorynios/Verilog HDL Files/jtag_uart.v
memorynios/Verilog HDL Files/led_pio.v
memorynios/Verilog HDL Files/memorynios.v
memorynios/Verilog HDL Files/memorynios_inst.v
memorynios/Verilog HDL Files/reset_counter.v
memorynios/Verilog HDL Files/sd_pll.v
memorynios/Verilog HDL Files/sram_16bit_512k_0.v
memorynios/Verilog HDL Files/sysid.v
memorynios/software/flash_test_simple_0
memorynios/software/hello_led_0
memorynios/SRAM/hdl
memorynios/software
memorynios/SRAM
memorynios/Verilog HDL Files
memorynios
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