文件名称:EMAC6
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- 上传时间:2013-01-13
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文件大小:3.44mb
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已下载:2次
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verilog实现的FPGA三态以太网链路层通信代码,里面有状态机,并按各个模块的功能分了文件夹,还有说明文档,自定义帧的产生和接收,开发环境为Xilinx ISE,测试无误。-verilog realization FPGA Tri-Mode Ethernet link layer communication code, which the state machine, according to the function of each module sub folder, as well as documentation, self-defined frame generation and reception, the development environment for the Xilinx ISEtest and correct.
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下载文件列表
EMAC6/
EMAC6/EMAC6.cgc
EMAC6/EMAC6.cgp
EMAC6/tmp/
EMAC6/tmp/_cg/
EMAC6/tmp/_xmsgs/
EMAC6/tmp/_xmsgs/netgen.xmsgs
EMAC6/tmp/_xmsgs/ngcbuild.xmsgs
EMAC6/tmp/_xmsgs/pn_parser.xmsgs
EMAC6/tmp/_xmsgs/xst.xmsgs
EMAC6/v6_emac_v2_1/
EMAC6/v6_emac_v2_1/doc/
EMAC6/v6_emac_v2_1/doc/ds835_v6_emac.pdf
EMAC6/v6_emac_v2_1/doc/ug800_v6_emac.pdf
EMAC6/v6_emac_v2_1/example_design/
EMAC6/v6_emac_v2_1/example_design/axi_ipif/
EMAC6/v6_emac_v2_1/example_design/axi_ipif/address_decoder.v
EMAC6/v6_emac_v2_1/example_design/axi_ipif/axi4_lite_ipif_wrapper.v
EMAC6/v6_emac_v2_1/example_design/axi_ipif/axi_lite_ipif.v
EMAC6/v6_emac_v2_1/example_design/axi_ipif/counter_f.v
EMAC6/v6_emac_v2_1/example_design/axi_ipif/pselect_f.v
EMAC6/v6_emac_v2_1/example_design/axi_ipif/slave_attachment.v
EMAC6/v6_emac_v2_1/example_design/axi_lite/
EMAC6/v6_emac_v2_1/example_design/axi_lite/axi_lite_sm.v
EMAC6/v6_emac_v2_1/example_design/clk_wiz.v
EMAC6/v6_emac_v2_1/example_design/common/
EMAC6/v6_emac_v2_1/example_design/common/reset_sync.v
EMAC6/v6_emac_v2_1/example_design/common/sync_block.v
EMAC6/v6_emac_v2_1/example_design/fifo/
EMAC6/v6_emac_v2_1/example_design/fifo/rx_client_fifo.v
EMAC6/v6_emac_v2_1/example_design/fifo/ten_100_1g_eth_fifo.v
EMAC6/v6_emac_v2_1/example_design/fifo/tx_client_fifo.v
EMAC6/v6_emac_v2_1/example_design/pat_gen/
EMAC6/v6_emac_v2_1/example_design/pat_gen/address_swap.v
EMAC6/v6_emac_v2_1/example_design/pat_gen/axi_mux.v
EMAC6/v6_emac_v2_1/example_design/pat_gen/axi_pat_check.v
EMAC6/v6_emac_v2_1/example_design/pat_gen/axi_pat_gen.v
EMAC6/v6_emac_v2_1/example_design/pat_gen/axi_pipe.v
EMAC6/v6_emac_v2_1/example_design/pat_gen/basic_pat_gen.v
EMAC6/v6_emac_v2_1/example_design/physical/
EMAC6/v6_emac_v2_1/example_design/physical/gmii_if.v
EMAC6/v6_emac_v2_1/example_design/statistics/
EMAC6/v6_emac_v2_1/example_design/statistics/vector_decode.v
EMAC6/v6_emac_v2_1/example_design/v6_emac_v2_1_block.v
EMAC6/v6_emac_v2_1/example_design/v6_emac_v2_1_example_design.ucf
EMAC6/v6_emac_v2_1/example_design/v6_emac_v2_1_example_design.v
EMAC6/v6_emac_v2_1/example_design/v6_emac_v2_1_fifo_block.v
EMAC6/v6_emac_v2_1/example_design/v6_emac_v2_1_mod.v
EMAC6/v6_emac_v2_1/implement/
EMAC6/v6_emac_v2_1/implement/implement.bat
EMAC6/v6_emac_v2_1/implement/implement.sh
EMAC6/v6_emac_v2_1/implement/xst.prj
EMAC6/v6_emac_v2_1/implement/xst.scr
EMAC6/v6_emac_v2_1/simulation/
EMAC6/v6_emac_v2_1/simulation/demo_tb.v
EMAC6/v6_emac_v2_1/simulation/functional/
EMAC6/v6_emac_v2_1/simulation/functional/simulate_mti.do
EMAC6/v6_emac_v2_1/simulation/functional/simulate_ncsim.sh
EMAC6/v6_emac_v2_1/simulation/functional/simulate_vcs.sh
EMAC6/v6_emac_v2_1/simulation/functional/ucli_commands.key
EMAC6/v6_emac_v2_1/simulation/functional/vcs_session.tcl
EMAC6/v6_emac_v2_1/simulation/functional/wave_mti.do
EMAC6/v6_emac_v2_1/simulation/functional/wave_ncsim.sv
EMAC6/v6_emac_v2_1/simulation/mdio_tb.v
EMAC6/v6_emac_v2_1/simulation/phy_tb.v
EMAC6/v6_emac_v2_1/simulation/timing/
EMAC6/v6_emac_v2_1/simulation/timing/simulate_mti.do
EMAC6/v6_emac_v2_1/simulation/timing/simulate_ncsim.sh
EMAC6/v6_emac_v2_1/simulation/timing/simulate_vcs.sh
EMAC6/v6_emac_v2_1/simulation/timing/ucli_commands.key
EMAC6/v6_emac_v2_1/simulation/timing/vcs_session.tcl
EMAC6/v6_emac_v2_1/simulation/timing/wave_mti.do
EMAC6/v6_emac_v2_1/simulation/timing/wave_ncsim.sv
EMAC6/v6_emac_v2_1/v6_emac_readme.txt
EMAC6/v6_emac_v2_1.asy
EMAC6/v6_emac_v2_1.gise
EMAC6/v6_emac_v2_1.ngc
EMAC6/v6_emac_v2_1.v
EMAC6/v6_emac_v2_1.veo
EMAC6/v6_emac_v2_1.xco
EMAC6/v6_emac_v2_1.xise
EMAC6/v6_emac_v2_1_emac_wrapper_1.lso
EMAC6/v6_emac_v2_1_flist.txt
EMAC6/v6_emac_v2_1_xmdf.tcl
EMAC6/xlnx_auto_0_xdb/
EMAC6/EMAC6.cgc
EMAC6/EMAC6.cgp
EMAC6/tmp/
EMAC6/tmp/_cg/
EMAC6/tmp/_xmsgs/
EMAC6/tmp/_xmsgs/netgen.xmsgs
EMAC6/tmp/_xmsgs/ngcbuild.xmsgs
EMAC6/tmp/_xmsgs/pn_parser.xmsgs
EMAC6/tmp/_xmsgs/xst.xmsgs
EMAC6/v6_emac_v2_1/
EMAC6/v6_emac_v2_1/doc/
EMAC6/v6_emac_v2_1/doc/ds835_v6_emac.pdf
EMAC6/v6_emac_v2_1/doc/ug800_v6_emac.pdf
EMAC6/v6_emac_v2_1/example_design/
EMAC6/v6_emac_v2_1/example_design/axi_ipif/
EMAC6/v6_emac_v2_1/example_design/axi_ipif/address_decoder.v
EMAC6/v6_emac_v2_1/example_design/axi_ipif/axi4_lite_ipif_wrapper.v
EMAC6/v6_emac_v2_1/example_design/axi_ipif/axi_lite_ipif.v
EMAC6/v6_emac_v2_1/example_design/axi_ipif/counter_f.v
EMAC6/v6_emac_v2_1/example_design/axi_ipif/pselect_f.v
EMAC6/v6_emac_v2_1/example_design/axi_ipif/slave_attachment.v
EMAC6/v6_emac_v2_1/example_design/axi_lite/
EMAC6/v6_emac_v2_1/example_design/axi_lite/axi_lite_sm.v
EMAC6/v6_emac_v2_1/example_design/clk_wiz.v
EMAC6/v6_emac_v2_1/example_design/common/
EMAC6/v6_emac_v2_1/example_design/common/reset_sync.v
EMAC6/v6_emac_v2_1/example_design/common/sync_block.v
EMAC6/v6_emac_v2_1/example_design/fifo/
EMAC6/v6_emac_v2_1/example_design/fifo/rx_client_fifo.v
EMAC6/v6_emac_v2_1/example_design/fifo/ten_100_1g_eth_fifo.v
EMAC6/v6_emac_v2_1/example_design/fifo/tx_client_fifo.v
EMAC6/v6_emac_v2_1/example_design/pat_gen/
EMAC6/v6_emac_v2_1/example_design/pat_gen/address_swap.v
EMAC6/v6_emac_v2_1/example_design/pat_gen/axi_mux.v
EMAC6/v6_emac_v2_1/example_design/pat_gen/axi_pat_check.v
EMAC6/v6_emac_v2_1/example_design/pat_gen/axi_pat_gen.v
EMAC6/v6_emac_v2_1/example_design/pat_gen/axi_pipe.v
EMAC6/v6_emac_v2_1/example_design/pat_gen/basic_pat_gen.v
EMAC6/v6_emac_v2_1/example_design/physical/
EMAC6/v6_emac_v2_1/example_design/physical/gmii_if.v
EMAC6/v6_emac_v2_1/example_design/statistics/
EMAC6/v6_emac_v2_1/example_design/statistics/vector_decode.v
EMAC6/v6_emac_v2_1/example_design/v6_emac_v2_1_block.v
EMAC6/v6_emac_v2_1/example_design/v6_emac_v2_1_example_design.ucf
EMAC6/v6_emac_v2_1/example_design/v6_emac_v2_1_example_design.v
EMAC6/v6_emac_v2_1/example_design/v6_emac_v2_1_fifo_block.v
EMAC6/v6_emac_v2_1/example_design/v6_emac_v2_1_mod.v
EMAC6/v6_emac_v2_1/implement/
EMAC6/v6_emac_v2_1/implement/implement.bat
EMAC6/v6_emac_v2_1/implement/implement.sh
EMAC6/v6_emac_v2_1/implement/xst.prj
EMAC6/v6_emac_v2_1/implement/xst.scr
EMAC6/v6_emac_v2_1/simulation/
EMAC6/v6_emac_v2_1/simulation/demo_tb.v
EMAC6/v6_emac_v2_1/simulation/functional/
EMAC6/v6_emac_v2_1/simulation/functional/simulate_mti.do
EMAC6/v6_emac_v2_1/simulation/functional/simulate_ncsim.sh
EMAC6/v6_emac_v2_1/simulation/functional/simulate_vcs.sh
EMAC6/v6_emac_v2_1/simulation/functional/ucli_commands.key
EMAC6/v6_emac_v2_1/simulation/functional/vcs_session.tcl
EMAC6/v6_emac_v2_1/simulation/functional/wave_mti.do
EMAC6/v6_emac_v2_1/simulation/functional/wave_ncsim.sv
EMAC6/v6_emac_v2_1/simulation/mdio_tb.v
EMAC6/v6_emac_v2_1/simulation/phy_tb.v
EMAC6/v6_emac_v2_1/simulation/timing/
EMAC6/v6_emac_v2_1/simulation/timing/simulate_mti.do
EMAC6/v6_emac_v2_1/simulation/timing/simulate_ncsim.sh
EMAC6/v6_emac_v2_1/simulation/timing/simulate_vcs.sh
EMAC6/v6_emac_v2_1/simulation/timing/ucli_commands.key
EMAC6/v6_emac_v2_1/simulation/timing/vcs_session.tcl
EMAC6/v6_emac_v2_1/simulation/timing/wave_mti.do
EMAC6/v6_emac_v2_1/simulation/timing/wave_ncsim.sv
EMAC6/v6_emac_v2_1/v6_emac_readme.txt
EMAC6/v6_emac_v2_1.asy
EMAC6/v6_emac_v2_1.gise
EMAC6/v6_emac_v2_1.ngc
EMAC6/v6_emac_v2_1.v
EMAC6/v6_emac_v2_1.veo
EMAC6/v6_emac_v2_1.xco
EMAC6/v6_emac_v2_1.xise
EMAC6/v6_emac_v2_1_emac_wrapper_1.lso
EMAC6/v6_emac_v2_1_flist.txt
EMAC6/v6_emac_v2_1_xmdf.tcl
EMAC6/xlnx_auto_0_xdb/
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