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文件名称:lab4

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  • 上传时间:
    2013-01-14
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    1.99mb
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使用赛灵思的EDK、SDK开发环境编写的微处理器内核,包括整个工程所需要的全部源代码。-Microprocessor core using the Xilinx EDK, SDK development environment written, all the source code needed to include the entire project.
(系统自动生成,下载前可以参看下载内容)

下载文件列表

lab4/
lab4/Alu.lso
lab4/Alu.prj
lab4/Alu.stx
lab4/Alu.v
lab4/Alu.xst
lab4/aluCtr.lso
lab4/aluCtr.prj
lab4/aluCtr.stx
lab4/aluCtr.v
lab4/aluCtr.xst
lab4/aluCtr_stx_beh.prj
lab4/Alu_stx_beh.prj
lab4/ctr.bmm
lab4/ctr.lso
lab4/ctr.prj
lab4/ctr.stx
lab4/ctr.v
lab4/ctr.xst
lab4/ctr_stx_beh.prj
lab4/fuse.log
lab4/fuse.xmsgs
lab4/fuseRelaunch.cmd
lab4/ipcore_dir/
lab4/ipcore_dir/coregen.cgp
lab4/ipcore_dir/coregen.log
lab4/ipcore_dir/create_dram.tcl
lab4/ipcore_dir/create_irom.tcl
lab4/ipcore_dir/dist_mem_gen_ds322.pdf
lab4/ipcore_dir/dist_mem_gen_v6_2_readme.txt
lab4/ipcore_dir/dram.asy
lab4/ipcore_dir/dram.gise
lab4/ipcore_dir/dram.ncf
lab4/ipcore_dir/dram.ngc
lab4/ipcore_dir/dram.sym
lab4/ipcore_dir/dram.v
lab4/ipcore_dir/dram.veo
lab4/ipcore_dir/dram.xco
lab4/ipcore_dir/dram.xise
lab4/ipcore_dir/dram_flist.txt
lab4/ipcore_dir/dram_ste/
lab4/ipcore_dir/dram_ste/example_design/
lab4/ipcore_dir/dram_ste/example_design/dram_top.ucf
lab4/ipcore_dir/dram_ste/example_design/dram_top.vhd
lab4/ipcore_dir/dram_ste/example_design/dram_top.xdc
lab4/ipcore_dir/dram_ste/implement/
lab4/ipcore_dir/dram_ste/implement/implement.bat
lab4/ipcore_dir/dram_ste/implement/implement.sh
lab4/ipcore_dir/dram_ste/implement/planAhead_rdn.bat
lab4/ipcore_dir/dram_ste/implement/planAhead_rdn.sh
lab4/ipcore_dir/dram_ste/implement/planAhead_rdn.tcl
lab4/ipcore_dir/dram_ste/implement/xst.prj
lab4/ipcore_dir/dram_ste/implement/xst.scr
lab4/ipcore_dir/dram_xmdf.tcl
lab4/ipcore_dir/edit_dram.tcl
lab4/ipcore_dir/edit_irom.tcl
lab4/ipcore_dir/irom.asy
lab4/ipcore_dir/irom.gise
lab4/ipcore_dir/irom.mif
lab4/ipcore_dir/irom.ncf
lab4/ipcore_dir/irom.ngc
lab4/ipcore_dir/irom.sym
lab4/ipcore_dir/irom.v
lab4/ipcore_dir/irom.veo
lab4/ipcore_dir/irom.xco
lab4/ipcore_dir/irom.xise
lab4/ipcore_dir/irom_flist.txt
lab4/ipcore_dir/irom_ste/
lab4/ipcore_dir/irom_ste/example_design/
lab4/ipcore_dir/irom_ste/example_design/irom_top.ucf
lab4/ipcore_dir/irom_ste/example_design/irom_top.vhd
lab4/ipcore_dir/irom_ste/example_design/irom_top.xdc
lab4/ipcore_dir/irom_ste/implement/
lab4/ipcore_dir/irom_ste/implement/implement.bat
lab4/ipcore_dir/irom_ste/implement/implement.sh
lab4/ipcore_dir/irom_ste/implement/planAhead_rdn.bat
lab4/ipcore_dir/irom_ste/implement/planAhead_rdn.sh
lab4/ipcore_dir/irom_ste/implement/planAhead_rdn.tcl
lab4/ipcore_dir/irom_ste/implement/xst.prj
lab4/ipcore_dir/irom_ste/implement/xst.scr
lab4/ipcore_dir/irom_xmdf.tcl
lab4/ipcore_dir/tmp/
lab4/ipcore_dir/tmp/dram.lso
lab4/ipcore_dir/tmp/irom.lso
lab4/ipcore_dir/tmp/xlnx_auto_0_xdb/
lab4/ipcore_dir/tmp/_cg/
lab4/ipcore_dir/tmp/_xmsgs/
lab4/ipcore_dir/tmp/_xmsgs/ngcbuild.xmsgs
lab4/ipcore_dir/tmp/_xmsgs/pn_parser.xmsgs
lab4/ipcore_dir/tmp/_xmsgs/xst.xmsgs
lab4/ipcore_dir/_xmsgs/
lab4/ipcore_dir/_xmsgs/cg.xmsgs
lab4/ipcore_dir/_xmsgs/pn_parser.xmsgs
lab4/irom.mif
lab4/iseconfig/
lab4/iseconfig/lab3.projectmgr
lab4/iseconfig/TOP.xreport
lab4/isim/
lab4/isim.cmd
lab4/isim.log
lab4/isim/isim_usage_statistics.html
lab4/isim/pn_info
lab4/isim/switch_isim_beh.exe.sim/
lab4/isim/switch_isim_beh.exe.sim/isimcrash.log
lab4/isim/switch_isim_beh.exe.sim/ISimEngine-DesignHierarchy.dbg
lab4/isim/switch_isim_beh.exe.sim/isimkernel.log
lab4/isim/switch_isim_beh.exe.sim/netId.dat
lab4/isim/switch_isim_beh.exe.sim/switch_isim_beh.exe
lab4/isim/switch_isim_beh.exe.sim/tmp_save/
lab4/isim/switch_isim_beh.exe.sim/tmp_save/_1
lab4/isim/switch_isim_beh.exe.sim/work/
lab4/isim/switch_isim_beh.exe.sim/work/m_00000000000826732639_0141691302.c
lab4/isim/switch_isim_beh.exe.sim/work/m_00000000000826732639_0141691302.didat
lab4/isim/switch_isim_beh.exe.sim/work/m_00000000000826732639_0141691302.nt.obj
lab4/isim/switch_isim_beh.exe.sim/work/m_00000000004134447467_2073120511.c
lab4/isim/switch_isim_beh.exe.sim/work/m_00000000004134447467_2073120511.didat
lab4/isim/switch_isim_beh.exe.sim/work/m_00000000004134447467_2073120511.nt.obj
lab4/isim/switch_isim_beh.exe.sim/work/switch_isim_beh.exe_main.c
lab4/isim/switch_isim_beh.exe.sim/work/switch_isim_beh.exe_main.nt.obj
lab4/isim/temp/
lab4/isim/temp/@alu.sdb
lab4/isim/temp/@t@o@p.sdb
lab4/isim/temp/alu@ctr.sdb
lab4/isim/temp/ctr.sdb
lab4/isim/temp/dram.sdb
lab4/isim/temp/glbl.sdb
lab4/isim/temp/irom.sdb
lab4/isim/temp/led.sdb
lab4/isim/temp/reg@file.sdb
lab4/isim/temp/signedxt.sdb
lab4/isim/temp/switch.sdb
lab4/isim/TOP_isim_beh.exe.sim/
lab4/isim/TOP_isim_beh.exe.sim/isimcrash.log
lab4/isim/TOP_isim_beh.exe.sim/ISimEngine-DesignHierarchy.dbg
lab4/isim/TOP_isim_beh.exe.sim/isimkernel.log
lab4/isim/TOP_isim_beh.exe.sim/netId.dat
lab4/isim/TOP_isim_beh.exe.sim/tmp_save/
lab4/isim/TOP_isim_beh.exe.sim/tmp_save/_1
lab4/isim/TOP_isim_beh.exe.sim/TOP_isim_beh.exe
lab4/isim/TOP_isim_beh.exe.sim/work/
lab4/isim/TOP_isim_beh.exe.sim/work/m_00000000000333124884_3180292034.c
lab4/isim/TOP_isim_beh.exe.sim/work/m_00000000000333124884_3180292034.didat
lab4/isim/TOP_isim_beh.exe.sim/work/m_00000000000333124884_3180292034.nt.obj
lab4/isim/TOP_isim_beh.exe.sim/work/m_00000000000538716681_1970878987.c
lab4/isim/TOP_isim_beh.exe.sim/work/m_00000000000538716681_1970878987.didat
lab4/isim/TOP_isim_beh.exe.sim/work/

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