文件名称:choose8_1
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- 上传时间:2013-01-21
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文件大小:149.55kb
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8选一选择器的verilog实现,运行通过仿真!-8 election selector verilog implementation, running through simulation!
(系统自动生成,下载前可以参看下载内容)
下载文件列表
choose8_1/
choose8_1/choose8_1.done
choose8_1/choose8_1.eda.rpt
choose8_1/choose8_1.flow.rpt
choose8_1/choose8_1.map.rpt
choose8_1/choose8_1.map.smsg
choose8_1/choose8_1.map.summary
choose8_1/choose8_1.qpf
choose8_1/choose8_1.qsf
choose8_1/choose8_1.v
choose8_1/choose8_1.v.bak
choose8_1/choose8_1_nativelink_simulation.rpt
choose8_1/db/
choose8_1/db/choose8_1.(0).cnf.cdb
choose8_1/db/choose8_1.(0).cnf.hdb
choose8_1/db/choose8_1.atom_map.rvd
choose8_1/db/choose8_1.cbx.xml
choose8_1/db/choose8_1.cmp.rdb
choose8_1/db/choose8_1.cmp_merge.kpt
choose8_1/db/choose8_1.db_info
choose8_1/db/choose8_1.eda.qmsg
choose8_1/db/choose8_1.hier_info
choose8_1/db/choose8_1.hif
choose8_1/db/choose8_1.lpc.html
choose8_1/db/choose8_1.lpc.rdb
choose8_1/db/choose8_1.lpc.txt
choose8_1/db/choose8_1.map.bpm
choose8_1/db/choose8_1.map.cdb
choose8_1/db/choose8_1.map.hdb
choose8_1/db/choose8_1.map.kpt
choose8_1/db/choose8_1.map.logdb
choose8_1/db/choose8_1.map.qmsg
choose8_1/db/choose8_1.map_bb.cdb
choose8_1/db/choose8_1.map_bb.hdb
choose8_1/db/choose8_1.map_bb.logdb
choose8_1/db/choose8_1.pre_map.cdb
choose8_1/db/choose8_1.pre_map.hdb
choose8_1/db/choose8_1.rpp.qmsg
choose8_1/db/choose8_1.rtlv.hdb
choose8_1/db/choose8_1.rtlv_sg.cdb
choose8_1/db/choose8_1.rtlv_sg_swap.cdb
choose8_1/db/choose8_1.sgate.rvd
choose8_1/db/choose8_1.sgate_sm.rvd
choose8_1/db/choose8_1.sgdiff.cdb
choose8_1/db/choose8_1.sgdiff.hdb
choose8_1/db/choose8_1.sld_design_entry.sci
choose8_1/db/choose8_1.sld_design_entry_dsc.sci
choose8_1/db/choose8_1.smart_action.txt
choose8_1/db/choose8_1.syn_hier_info
choose8_1/db/choose8_1.tis_db_list.ddb
choose8_1/db/choose8_1.tmw_info
choose8_1/db/logic_util_heursitic.dat
choose8_1/db/prev_cmp_choose8_1.qmsg
choose8_1/incremental_db/
choose8_1/incremental_db/README
choose8_1/incremental_db/compiled_partitions/
choose8_1/incremental_db/compiled_partitions/choose8_1.db_info
choose8_1/incremental_db/compiled_partitions/choose8_1.root_partition.map.cdb
choose8_1/incremental_db/compiled_partitions/choose8_1.root_partition.map.dpi
choose8_1/incremental_db/compiled_partitions/choose8_1.root_partition.map.hbdb.cdb
choose8_1/incremental_db/compiled_partitions/choose8_1.root_partition.map.hbdb.hb_info
choose8_1/incremental_db/compiled_partitions/choose8_1.root_partition.map.hbdb.hdb
choose8_1/incremental_db/compiled_partitions/choose8_1.root_partition.map.hbdb.sig
choose8_1/incremental_db/compiled_partitions/choose8_1.root_partition.map.hdb
choose8_1/incremental_db/compiled_partitions/choose8_1.root_partition.map.kpt
choose8_1/simulation/
choose8_1/simulation/modelsim/
choose8_1/simulation/modelsim/choose8_1.vt
choose8_1/simulation/modelsim/choose8_1.vt.bak
choose8_1/simulation/modelsim/choose8_1_run_msim_rtl_verilog.do
choose8_1/simulation/modelsim/choose8_1_run_msim_rtl_verilog.do.bak
choose8_1/simulation/modelsim/choose8_1_run_msim_rtl_verilog.do.bak1
choose8_1/simulation/modelsim/choose8_1_run_msim_rtl_verilog.do.bak2
choose8_1/simulation/modelsim/choose8_1_run_msim_rtl_verilog.do.bak3
choose8_1/simulation/modelsim/modelsim.ini
choose8_1/simulation/modelsim/msim_transcript
choose8_1/simulation/modelsim/rtl_work/
choose8_1/simulation/modelsim/rtl_work/_info
choose8_1/simulation/modelsim/rtl_work/_temp/
choose8_1/simulation/modelsim/rtl_work/_vmake
choose8_1/simulation/modelsim/rtl_work/choose8_1/
choose8_1/simulation/modelsim/rtl_work/choose8_1/_primary.dat
choose8_1/simulation/modelsim/rtl_work/choose8_1/_primary.dbs
choose8_1/simulation/modelsim/rtl_work/choose8_1/_primary.vhd
choose8_1/simulation/modelsim/rtl_work/choose8_1/verilog.prw
choose8_1/simulation/modelsim/rtl_work/choose8_1/verilog.psm
choose8_1/simulation/modelsim/rtl_work/choose8_1_vlg_tst/
choose8_1/simulation/modelsim/rtl_work/choose8_1_vlg_tst/_primary.dat
choose8_1/simulation/modelsim/rtl_work/choose8_1_vlg_tst/_primary.dbs
choose8_1/simulation/modelsim/rtl_work/choose8_1_vlg_tst/_primary.vhd
choose8_1/simulation/modelsim/rtl_work/choose8_1_vlg_tst/verilog.prw
choose8_1/simulation/modelsim/rtl_work/choose8_1_vlg_tst/verilog.psm
choose8_1/simulation/modelsim/vsim.wlf
choose8_1/choose8_1.done
choose8_1/choose8_1.eda.rpt
choose8_1/choose8_1.flow.rpt
choose8_1/choose8_1.map.rpt
choose8_1/choose8_1.map.smsg
choose8_1/choose8_1.map.summary
choose8_1/choose8_1.qpf
choose8_1/choose8_1.qsf
choose8_1/choose8_1.v
choose8_1/choose8_1.v.bak
choose8_1/choose8_1_nativelink_simulation.rpt
choose8_1/db/
choose8_1/db/choose8_1.(0).cnf.cdb
choose8_1/db/choose8_1.(0).cnf.hdb
choose8_1/db/choose8_1.atom_map.rvd
choose8_1/db/choose8_1.cbx.xml
choose8_1/db/choose8_1.cmp.rdb
choose8_1/db/choose8_1.cmp_merge.kpt
choose8_1/db/choose8_1.db_info
choose8_1/db/choose8_1.eda.qmsg
choose8_1/db/choose8_1.hier_info
choose8_1/db/choose8_1.hif
choose8_1/db/choose8_1.lpc.html
choose8_1/db/choose8_1.lpc.rdb
choose8_1/db/choose8_1.lpc.txt
choose8_1/db/choose8_1.map.bpm
choose8_1/db/choose8_1.map.cdb
choose8_1/db/choose8_1.map.hdb
choose8_1/db/choose8_1.map.kpt
choose8_1/db/choose8_1.map.logdb
choose8_1/db/choose8_1.map.qmsg
choose8_1/db/choose8_1.map_bb.cdb
choose8_1/db/choose8_1.map_bb.hdb
choose8_1/db/choose8_1.map_bb.logdb
choose8_1/db/choose8_1.pre_map.cdb
choose8_1/db/choose8_1.pre_map.hdb
choose8_1/db/choose8_1.rpp.qmsg
choose8_1/db/choose8_1.rtlv.hdb
choose8_1/db/choose8_1.rtlv_sg.cdb
choose8_1/db/choose8_1.rtlv_sg_swap.cdb
choose8_1/db/choose8_1.sgate.rvd
choose8_1/db/choose8_1.sgate_sm.rvd
choose8_1/db/choose8_1.sgdiff.cdb
choose8_1/db/choose8_1.sgdiff.hdb
choose8_1/db/choose8_1.sld_design_entry.sci
choose8_1/db/choose8_1.sld_design_entry_dsc.sci
choose8_1/db/choose8_1.smart_action.txt
choose8_1/db/choose8_1.syn_hier_info
choose8_1/db/choose8_1.tis_db_list.ddb
choose8_1/db/choose8_1.tmw_info
choose8_1/db/logic_util_heursitic.dat
choose8_1/db/prev_cmp_choose8_1.qmsg
choose8_1/incremental_db/
choose8_1/incremental_db/README
choose8_1/incremental_db/compiled_partitions/
choose8_1/incremental_db/compiled_partitions/choose8_1.db_info
choose8_1/incremental_db/compiled_partitions/choose8_1.root_partition.map.cdb
choose8_1/incremental_db/compiled_partitions/choose8_1.root_partition.map.dpi
choose8_1/incremental_db/compiled_partitions/choose8_1.root_partition.map.hbdb.cdb
choose8_1/incremental_db/compiled_partitions/choose8_1.root_partition.map.hbdb.hb_info
choose8_1/incremental_db/compiled_partitions/choose8_1.root_partition.map.hbdb.hdb
choose8_1/incremental_db/compiled_partitions/choose8_1.root_partition.map.hbdb.sig
choose8_1/incremental_db/compiled_partitions/choose8_1.root_partition.map.hdb
choose8_1/incremental_db/compiled_partitions/choose8_1.root_partition.map.kpt
choose8_1/simulation/
choose8_1/simulation/modelsim/
choose8_1/simulation/modelsim/choose8_1.vt
choose8_1/simulation/modelsim/choose8_1.vt.bak
choose8_1/simulation/modelsim/choose8_1_run_msim_rtl_verilog.do
choose8_1/simulation/modelsim/choose8_1_run_msim_rtl_verilog.do.bak
choose8_1/simulation/modelsim/choose8_1_run_msim_rtl_verilog.do.bak1
choose8_1/simulation/modelsim/choose8_1_run_msim_rtl_verilog.do.bak2
choose8_1/simulation/modelsim/choose8_1_run_msim_rtl_verilog.do.bak3
choose8_1/simulation/modelsim/modelsim.ini
choose8_1/simulation/modelsim/msim_transcript
choose8_1/simulation/modelsim/rtl_work/
choose8_1/simulation/modelsim/rtl_work/_info
choose8_1/simulation/modelsim/rtl_work/_temp/
choose8_1/simulation/modelsim/rtl_work/_vmake
choose8_1/simulation/modelsim/rtl_work/choose8_1/
choose8_1/simulation/modelsim/rtl_work/choose8_1/_primary.dat
choose8_1/simulation/modelsim/rtl_work/choose8_1/_primary.dbs
choose8_1/simulation/modelsim/rtl_work/choose8_1/_primary.vhd
choose8_1/simulation/modelsim/rtl_work/choose8_1/verilog.prw
choose8_1/simulation/modelsim/rtl_work/choose8_1/verilog.psm
choose8_1/simulation/modelsim/rtl_work/choose8_1_vlg_tst/
choose8_1/simulation/modelsim/rtl_work/choose8_1_vlg_tst/_primary.dat
choose8_1/simulation/modelsim/rtl_work/choose8_1_vlg_tst/_primary.dbs
choose8_1/simulation/modelsim/rtl_work/choose8_1_vlg_tst/_primary.vhd
choose8_1/simulation/modelsim/rtl_work/choose8_1_vlg_tst/verilog.prw
choose8_1/simulation/modelsim/rtl_work/choose8_1_vlg_tst/verilog.psm
choose8_1/simulation/modelsim/vsim.wlf
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