文件名称:fdivision
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- 上传时间:2013-01-25
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文件大小:9.52mb
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一个分频的quartus工程,用verilog写的,改变i的值可以实现任意分频,绝对原创-Quartus project a divide verilog write, change the value of i can achieve arbitrary divide absolute originality! ! !
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下载文件列表
fdivision/
fdivision/db/
fdivision/db/fdivision.(0).cnf.cdb
fdivision/db/fdivision.(0).cnf.hdb
fdivision/db/fdivision.atom_map.rvd
fdivision/db/fdivision.cbx.xml
fdivision/db/fdivision.cmp.rdb
fdivision/db/fdivision.cmp_merge.kpt
fdivision/db/fdivision.db_info
fdivision/db/fdivision.eda.qmsg
fdivision/db/fdivision.hier_info
fdivision/db/fdivision.hif
fdivision/db/fdivision.lpc.html
fdivision/db/fdivision.lpc.rdb
fdivision/db/fdivision.lpc.txt
fdivision/db/fdivision.map.bpm
fdivision/db/fdivision.map.cdb
fdivision/db/fdivision.map.hdb
fdivision/db/fdivision.map.kpt
fdivision/db/fdivision.map.logdb
fdivision/db/fdivision.map.qmsg
fdivision/db/fdivision.map_bb.cdb
fdivision/db/fdivision.map_bb.hdb
fdivision/db/fdivision.map_bb.logdb
fdivision/db/fdivision.pre_map.cdb
fdivision/db/fdivision.pre_map.hdb
fdivision/db/fdivision.rpp.qmsg
fdivision/db/fdivision.rtlv.hdb
fdivision/db/fdivision.rtlv_sg.cdb
fdivision/db/fdivision.rtlv_sg_swap.cdb
fdivision/db/fdivision.sgate.rvd
fdivision/db/fdivision.sgate_sm.rvd
fdivision/db/fdivision.sgdiff.cdb
fdivision/db/fdivision.sgdiff.hdb
fdivision/db/fdivision.sld_design_entry.sci
fdivision/db/fdivision.sld_design_entry_dsc.sci
fdivision/db/fdivision.smart_action.txt
fdivision/db/fdivision.syn_hier_info
fdivision/db/fdivision.tis_db_list.ddb
fdivision/db/fdivision.tmw_info
fdivision/db/logic_util_heursitic.dat
fdivision/db/prev_cmp_fdivision.qmsg
fdivision/fdivision.done
fdivision/fdivision.eda.rpt
fdivision/fdivision.flow.rpt
fdivision/fdivision.map.rpt
fdivision/fdivision.map.smsg
fdivision/fdivision.map.summary
fdivision/fdivision.qpf
fdivision/fdivision.qsf
fdivision/fdivision.v
fdivision/fdivision.v.bak
fdivision/fdivision_nativelink_simulation.rpt
fdivision/incremental_db/
fdivision/incremental_db/README
fdivision/incremental_db/compiled_partitions/
fdivision/incremental_db/compiled_partitions/fdivision.db_info
fdivision/incremental_db/compiled_partitions/fdivision.root_partition.map.cdb
fdivision/incremental_db/compiled_partitions/fdivision.root_partition.map.dpi
fdivision/incremental_db/compiled_partitions/fdivision.root_partition.map.hbdb.cdb
fdivision/incremental_db/compiled_partitions/fdivision.root_partition.map.hbdb.hb_info
fdivision/incremental_db/compiled_partitions/fdivision.root_partition.map.hbdb.hdb
fdivision/incremental_db/compiled_partitions/fdivision.root_partition.map.hbdb.sig
fdivision/incremental_db/compiled_partitions/fdivision.root_partition.map.hdb
fdivision/incremental_db/compiled_partitions/fdivision.root_partition.map.kpt
fdivision/simulation/
fdivision/simulation/modelsim/
fdivision/simulation/modelsim/fdivision.vt
fdivision/simulation/modelsim/fdivision.vt.bak
fdivision/simulation/modelsim/fdivision_run_msim_rtl_verilog.do
fdivision/simulation/modelsim/fdivision_run_msim_rtl_verilog.do.bak
fdivision/simulation/modelsim/fdivision_run_msim_rtl_verilog.do.bak1
fdivision/simulation/modelsim/fdivision_run_msim_rtl_verilog.do.bak10
fdivision/simulation/modelsim/fdivision_run_msim_rtl_verilog.do.bak11
fdivision/simulation/modelsim/fdivision_run_msim_rtl_verilog.do.bak2
fdivision/simulation/modelsim/fdivision_run_msim_rtl_verilog.do.bak3
fdivision/simulation/modelsim/fdivision_run_msim_rtl_verilog.do.bak4
fdivision/simulation/modelsim/fdivision_run_msim_rtl_verilog.do.bak5
fdivision/simulation/modelsim/fdivision_run_msim_rtl_verilog.do.bak6
fdivision/simulation/modelsim/fdivision_run_msim_rtl_verilog.do.bak7
fdivision/simulation/modelsim/fdivision_run_msim_rtl_verilog.do.bak8
fdivision/simulation/modelsim/fdivision_run_msim_rtl_verilog.do.bak9
fdivision/simulation/modelsim/modelsim.ini
fdivision/simulation/modelsim/msim_transcript
fdivision/simulation/modelsim/rtl_work/
fdivision/simulation/modelsim/rtl_work/_info
fdivision/simulation/modelsim/rtl_work/_temp/
fdivision/simulation/modelsim/rtl_work/_vmake
fdivision/simulation/modelsim/rtl_work/fdivision/
fdivision/simulation/modelsim/rtl_work/fdivision/_primary.dat
fdivision/simulation/modelsim/rtl_work/fdivision/_primary.dbs
fdivision/simulation/modelsim/rtl_work/fdivision/_primary.vhd
fdivision/simulation/modelsim/rtl_work/fdivision/verilog.prw
fdivision/simulation/modelsim/rtl_work/fdivision/verilog.psm
fdivision/simulation/modelsim/rtl_work/t/
fdivision/simulation/modelsim/rtl_work/t/_primary.dat
fdivision/simulation/modelsim/rtl_work/t/_primary.dbs
fdivision/simulation/modelsim/rtl_work/t/_primary.vhd
fdivision/simulation/modelsim/rtl_work/t/verilog.prw
fdivision/simulation/modelsim/rtl_work/t/verilog.psm
fdivision/simulation/modelsim/vsim.wlf
fdivision/db/
fdivision/db/fdivision.(0).cnf.cdb
fdivision/db/fdivision.(0).cnf.hdb
fdivision/db/fdivision.atom_map.rvd
fdivision/db/fdivision.cbx.xml
fdivision/db/fdivision.cmp.rdb
fdivision/db/fdivision.cmp_merge.kpt
fdivision/db/fdivision.db_info
fdivision/db/fdivision.eda.qmsg
fdivision/db/fdivision.hier_info
fdivision/db/fdivision.hif
fdivision/db/fdivision.lpc.html
fdivision/db/fdivision.lpc.rdb
fdivision/db/fdivision.lpc.txt
fdivision/db/fdivision.map.bpm
fdivision/db/fdivision.map.cdb
fdivision/db/fdivision.map.hdb
fdivision/db/fdivision.map.kpt
fdivision/db/fdivision.map.logdb
fdivision/db/fdivision.map.qmsg
fdivision/db/fdivision.map_bb.cdb
fdivision/db/fdivision.map_bb.hdb
fdivision/db/fdivision.map_bb.logdb
fdivision/db/fdivision.pre_map.cdb
fdivision/db/fdivision.pre_map.hdb
fdivision/db/fdivision.rpp.qmsg
fdivision/db/fdivision.rtlv.hdb
fdivision/db/fdivision.rtlv_sg.cdb
fdivision/db/fdivision.rtlv_sg_swap.cdb
fdivision/db/fdivision.sgate.rvd
fdivision/db/fdivision.sgate_sm.rvd
fdivision/db/fdivision.sgdiff.cdb
fdivision/db/fdivision.sgdiff.hdb
fdivision/db/fdivision.sld_design_entry.sci
fdivision/db/fdivision.sld_design_entry_dsc.sci
fdivision/db/fdivision.smart_action.txt
fdivision/db/fdivision.syn_hier_info
fdivision/db/fdivision.tis_db_list.ddb
fdivision/db/fdivision.tmw_info
fdivision/db/logic_util_heursitic.dat
fdivision/db/prev_cmp_fdivision.qmsg
fdivision/fdivision.done
fdivision/fdivision.eda.rpt
fdivision/fdivision.flow.rpt
fdivision/fdivision.map.rpt
fdivision/fdivision.map.smsg
fdivision/fdivision.map.summary
fdivision/fdivision.qpf
fdivision/fdivision.qsf
fdivision/fdivision.v
fdivision/fdivision.v.bak
fdivision/fdivision_nativelink_simulation.rpt
fdivision/incremental_db/
fdivision/incremental_db/README
fdivision/incremental_db/compiled_partitions/
fdivision/incremental_db/compiled_partitions/fdivision.db_info
fdivision/incremental_db/compiled_partitions/fdivision.root_partition.map.cdb
fdivision/incremental_db/compiled_partitions/fdivision.root_partition.map.dpi
fdivision/incremental_db/compiled_partitions/fdivision.root_partition.map.hbdb.cdb
fdivision/incremental_db/compiled_partitions/fdivision.root_partition.map.hbdb.hb_info
fdivision/incremental_db/compiled_partitions/fdivision.root_partition.map.hbdb.hdb
fdivision/incremental_db/compiled_partitions/fdivision.root_partition.map.hbdb.sig
fdivision/incremental_db/compiled_partitions/fdivision.root_partition.map.hdb
fdivision/incremental_db/compiled_partitions/fdivision.root_partition.map.kpt
fdivision/simulation/
fdivision/simulation/modelsim/
fdivision/simulation/modelsim/fdivision.vt
fdivision/simulation/modelsim/fdivision.vt.bak
fdivision/simulation/modelsim/fdivision_run_msim_rtl_verilog.do
fdivision/simulation/modelsim/fdivision_run_msim_rtl_verilog.do.bak
fdivision/simulation/modelsim/fdivision_run_msim_rtl_verilog.do.bak1
fdivision/simulation/modelsim/fdivision_run_msim_rtl_verilog.do.bak10
fdivision/simulation/modelsim/fdivision_run_msim_rtl_verilog.do.bak11
fdivision/simulation/modelsim/fdivision_run_msim_rtl_verilog.do.bak2
fdivision/simulation/modelsim/fdivision_run_msim_rtl_verilog.do.bak3
fdivision/simulation/modelsim/fdivision_run_msim_rtl_verilog.do.bak4
fdivision/simulation/modelsim/fdivision_run_msim_rtl_verilog.do.bak5
fdivision/simulation/modelsim/fdivision_run_msim_rtl_verilog.do.bak6
fdivision/simulation/modelsim/fdivision_run_msim_rtl_verilog.do.bak7
fdivision/simulation/modelsim/fdivision_run_msim_rtl_verilog.do.bak8
fdivision/simulation/modelsim/fdivision_run_msim_rtl_verilog.do.bak9
fdivision/simulation/modelsim/modelsim.ini
fdivision/simulation/modelsim/msim_transcript
fdivision/simulation/modelsim/rtl_work/
fdivision/simulation/modelsim/rtl_work/_info
fdivision/simulation/modelsim/rtl_work/_temp/
fdivision/simulation/modelsim/rtl_work/_vmake
fdivision/simulation/modelsim/rtl_work/fdivision/
fdivision/simulation/modelsim/rtl_work/fdivision/_primary.dat
fdivision/simulation/modelsim/rtl_work/fdivision/_primary.dbs
fdivision/simulation/modelsim/rtl_work/fdivision/_primary.vhd
fdivision/simulation/modelsim/rtl_work/fdivision/verilog.prw
fdivision/simulation/modelsim/rtl_work/fdivision/verilog.psm
fdivision/simulation/modelsim/rtl_work/t/
fdivision/simulation/modelsim/rtl_work/t/_primary.dat
fdivision/simulation/modelsim/rtl_work/t/_primary.dbs
fdivision/simulation/modelsim/rtl_work/t/_primary.vhd
fdivision/simulation/modelsim/rtl_work/t/verilog.prw
fdivision/simulation/modelsim/rtl_work/t/verilog.psm
fdivision/simulation/modelsim/vsim.wlf
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