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文件名称:fp_prj

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    2013-03-04
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    2.01mb
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这是自己编写的一个流水灯程序 通过修改cs的值可实现方向的翻转 但是没有接入案件功能 需要的同学可自行添加 使用quartus12编译 modelsim10.1仿真-This is a program I have written a light water can be achieved by modifying the value of cs direction flip but no access cases feature requires students own add use quartus12 compile modelsim10.1 simulation
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下载文件列表

fp_prj/db/fp_verilog.(0).cnf.cdb
fp_prj/db/fp_verilog.(0).cnf.hdb
fp_prj/db/fp_verilog.asm.qmsg
fp_prj/db/fp_verilog.asm.rdb
fp_prj/db/fp_verilog.cbx.xml
fp_prj/db/fp_verilog.cmp.bpm
fp_prj/db/fp_verilog.cmp.cdb
fp_prj/db/fp_verilog.cmp.hdb
fp_prj/db/fp_verilog.cmp.idb
fp_prj/db/fp_verilog.cmp.kpt
fp_prj/db/fp_verilog.cmp.logdb
fp_prj/db/fp_verilog.cmp.rdb
fp_prj/db/fp_verilog.cmp0.ddb
fp_prj/db/fp_verilog.cmp_merge.kpt
fp_prj/db/fp_verilog.db_info
fp_prj/db/fp_verilog.eda.qmsg
fp_prj/db/fp_verilog.fit.qmsg
fp_prj/db/fp_verilog.hier_info
fp_prj/db/fp_verilog.hif
fp_prj/db/fp_verilog.ipinfo
fp_prj/db/fp_verilog.lpc.html
fp_prj/db/fp_verilog.lpc.rdb
fp_prj/db/fp_verilog.lpc.txt
fp_prj/db/fp_verilog.map.bpm
fp_prj/db/fp_verilog.map.cdb
fp_prj/db/fp_verilog.map.hdb
fp_prj/db/fp_verilog.map.kpt
fp_prj/db/fp_verilog.map.logdb
fp_prj/db/fp_verilog.map.qmsg
fp_prj/db/fp_verilog.map.rdb
fp_prj/db/fp_verilog.map_bb.cdb
fp_prj/db/fp_verilog.map_bb.hdb
fp_prj/db/fp_verilog.map_bb.logdb
fp_prj/db/fp_verilog.pre_map.cdb
fp_prj/db/fp_verilog.pre_map.hdb
fp_prj/db/fp_verilog.qns
fp_prj/db/fp_verilog.root_partition.map.reg_db.cdb
fp_prj/db/fp_verilog.routing.rdb
fp_prj/db/fp_verilog.rtlv.hdb
fp_prj/db/fp_verilog.rtlv_sg.cdb
fp_prj/db/fp_verilog.rtlv_sg_swap.cdb
fp_prj/db/fp_verilog.sas
fp_prj/db/fp_verilog.sgdiff.cdb
fp_prj/db/fp_verilog.sgdiff.hdb
fp_prj/db/fp_verilog.sld_design_entry.sci
fp_prj/db/fp_verilog.sld_design_entry_dsc.sci
fp_prj/db/fp_verilog.smart_action.txt
fp_prj/db/fp_verilog.sta.qmsg
fp_prj/db/fp_verilog.sta.rdb
fp_prj/db/fp_verilog.sta_cmp.6_slow.tdb
fp_prj/db/fp_verilog.syn_hier_info
fp_prj/db/fp_verilog.tis_db_list.ddb
fp_prj/db/fp_verilog.tmw_info
fp_prj/db/fp_verilog.vpr.ammdb
fp_prj/db/fp_verilog_global_asgn_op.abo
fp_prj/db/logic_util_heursitic.dat
fp_prj/db/prev_cmp_fp_verilog.asm.qmsg
fp_prj/db/prev_cmp_fp_verilog.eda.qmsg
fp_prj/db/prev_cmp_fp_verilog.fit.qmsg
fp_prj/db/prev_cmp_fp_verilog.map.qmsg
fp_prj/db/prev_cmp_fp_verilog.qmsg
fp_prj/db/prev_cmp_fp_verilog.tan.qmsg
fp_prj/fp_verilog.asm.rpt
fp_prj/fp_verilog.cdf
fp_prj/fp_verilog.done
fp_prj/fp_verilog.eda.rpt
fp_prj/fp_verilog.fit.rpt
fp_prj/fp_verilog.fit.smsg
fp_prj/fp_verilog.fit.summary
fp_prj/fp_verilog.flow.rpt
fp_prj/fp_verilog.jdi
fp_prj/fp_verilog.map.rpt
fp_prj/fp_verilog.map.summary
fp_prj/fp_verilog.pin
fp_prj/fp_verilog.pof
fp_prj/fp_verilog.qpf
fp_prj/fp_verilog.qsf
fp_prj/fp_verilog.qws
fp_prj/fp_verilog.sof
fp_prj/fp_verilog.sta.rpt
fp_prj/fp_verilog.sta.summary
fp_prj/fp_verilog.tan.rpt
fp_prj/fp_verilog.tan.summary
fp_prj/fp_verilog.v
fp_prj/fp_verilog.v.bak
fp_prj/fp_verilog_assignment_defaults.qdf
fp_prj/fp_verilog_nativelink_simulation.rpt
fp_prj/incremental_db/compiled_partitions/fp_verilog.db_info
fp_prj/incremental_db/compiled_partitions/fp_verilog.root_partition.cmp.ammdb
fp_prj/incremental_db/compiled_partitions/fp_verilog.root_partition.cmp.cdb
fp_prj/incremental_db/compiled_partitions/fp_verilog.root_partition.cmp.dfp
fp_prj/incremental_db/compiled_partitions/fp_verilog.root_partition.cmp.hdb
fp_prj/incremental_db/compiled_partitions/fp_verilog.root_partition.cmp.kpt
fp_prj/incremental_db/compiled_partitions/fp_verilog.root_partition.cmp.logdb
fp_prj/incremental_db/compiled_partitions/fp_verilog.root_partition.cmp.rcfdb
fp_prj/incremental_db/compiled_partitions/fp_verilog.root_partition.map.cdb
fp_prj/incremental_db/compiled_partitions/fp_verilog.root_partition.map.dpi
fp_prj/incremental_db/compiled_partitions/fp_verilog.root_partition.map.hbdb.cdb
fp_prj/incremental_db/compiled_partitions/fp_verilog.root_partition.map.hbdb.hb_info
fp_prj/incremental_db/compiled_partitions/fp_verilog.root_partition.map.hbdb.hdb
fp_prj/incremental_db/compiled_partitions/fp_verilog.root_partition.map.hbdb.sig
fp_prj/incremental_db/compiled_partitions/fp_verilog.root_partition.map.hdb
fp_prj/incremental_db/compiled_partitions/fp_verilog.root_partition.map.kpt
fp_prj/incremental_db/README
fp_prj/quartus_nativelink_synthesis.log
fp_prj/simulation/modelsim/fp_verilog.sft
fp_prj/simulation/modelsim/fp_verilog.vo
fp_prj/simulation/modelsim/fp_verilog.vt
fp_prj/simulation/modelsim/fp_verilog.vt.bak
fp_prj/simulation/modelsim/fp_verilog_modelsim.xrf
fp_prj/simulation/modelsim/fp_verilog_run_msim_rtl_verilog.do
fp_prj/simulation/modelsim/fp_verilog_run_msim_rtl_verilog.do.bak
fp_prj/simulation/modelsim/fp_verilog_run_msim_rtl_verilog.do.bak1
fp_prj/simulation/modelsim/fp_verilog_run_msim_rtl_verilog.do.bak10
fp_prj/simulation/modelsim/fp_verilog_run_msim_rtl_verilog.do.bak11
fp_prj/simulation/modelsim/fp_verilog_run_msim_rtl_verilog.do.bak2
fp_prj/simulation/modelsim/fp_verilog_run_msim_rtl_verilog.do.bak3
fp_prj/simulation/modelsim/fp_verilog_run_msim_rtl_verilog.do.bak4
fp_prj/simulation/modelsim/fp_verilog_run_msim_rtl_verilog.do.bak5
fp_prj/simulation/modelsim/fp_verilog_run_msim_rtl_verilog.do.bak6
fp_prj/simulation/modelsim/fp_verilog_run_msim_rtl_verilog.do.bak7
fp_prj/simulation/modelsim/fp_verilog_run_msim_rtl_verilog.do.bak8
fp_prj/simulation/modelsim/fp_verilog_run_msim_rtl_verilog.do.bak9
fp_prj/simulation/modelsim/fp_verilog_v.sdo
fp_prj/simula

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