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文件名称:electric-current-

  • 所属分类：
    VHDL-FPGA-Verilog
  • 标签属性：
    [VHDL] [源码]
  • 上传时间：
    2013-03-08
  • 文件大小：
    1.34mb
  • 已下载：
    0次
  • 提 供 者：
    x****
  • 相关连接：
    无
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修正介绍说明

介绍说明－－下载内容来自于网络，使用问题请自行百度

周立功Fusion StartKit，fpga开发板的实验例程，电流监控实验-ZLG Fusion StartKit, fpga development board test routines, current monitoring experiments
(系统自动生成,下载前可以参看下载内容)

下载文件列表

电流监控实验/Project/CurrentMonitor_lab/constraint/CurrentMonitor_top.pdc
电流监控实验/Project/CurrentMonitor_lab/constraint/CurrentMonitor_top_sdc.sdc
电流监控实验/Project/CurrentMonitor_lab/CurrentMonitor_lab.prj
电流监控实验/Project/CurrentMonitor_lab/designer/impl1/CurrentMonitor_top.adb
电流监控实验/Project/CurrentMonitor_lab/designer/impl1/CurrentMonitor_top.dtf/verify.log
电流监控实验/Project/CurrentMonitor_lab/designer/impl1/CurrentMonitor_top.ide_des
电流监控实验/Project/CurrentMonitor_lab/designer/impl1/CurrentMonitor_top.pdb
电流监控实验/Project/CurrentMonitor_lab/designer/impl1/CurrentMonitor_top.pdb.depends
电流监控实验/Project/CurrentMonitor_lab/designer/impl1/CurrentMonitor_top.stp
电流监控实验/Project/CurrentMonitor_lab/designer/impl1/CurrentMonitor_top.tcl
电流监控实验/Project/CurrentMonitor_lab/designer/impl1/CurrentMonitor_top_ba.sdf
电流监控实验/Project/CurrentMonitor_lab/designer/impl1/CurrentMonitor_top_ba.v
电流监控实验/Project/CurrentMonitor_lab/designer/impl1/designer.log
电流监控实验/Project/CurrentMonitor_lab/designer/impl1/designer_genhdl.log
电流监控实验/Project/CurrentMonitor_lab/hdl/CurrentMonitor_top.v
电流监控实验/Project/CurrentMonitor_lab/hdl/hdlsynchk.tcl
电流监控实验/Project/CurrentMonitor_lab/simulation/analog_acm_ram_R0C0.mem
电流监控实验/Project/CurrentMonitor_lab/simulation/analog_assc_ram_R0C0.mem
电流监控实验/Project/CurrentMonitor_lab/simulation/analog_smev_ram_R0C0.mem
电流监控实验/Project/CurrentMonitor_lab/simulation/analog_smtr_ram_R0C0.mem
电流监控实验/Project/CurrentMonitor_lab/simulation/flashmem.mem
电流监控实验/Project/CurrentMonitor_lab/simulation/meminit.dat
电流监控实验/Project/CurrentMonitor_lab/simulation/modelsim.ini
电流监控实验/Project/CurrentMonitor_lab/simulation/modelsim.ini.sav
电流监控实验/Project/CurrentMonitor_lab/smartgen/analog/analog.cfg
电流监控实验/Project/CurrentMonitor_lab/smartgen/analog/analog.cxf
电流监控实验/Project/CurrentMonitor_lab/smartgen/analog/analog.gen
电流监控实验/Project/CurrentMonitor_lab/smartgen/analog/analog.log
电流监控实验/Project/CurrentMonitor_lab/smartgen/analog/analog.ncf
电流监控实验/Project/CurrentMonitor_lab/smartgen/analog/analog.v
电流监控实验/Project/CurrentMonitor_lab/smartgen/analog/analog_acm.mem
电流监控实验/Project/CurrentMonitor_lab/smartgen/analog/analog_acm_ram.hex
电流监控实验/Project/CurrentMonitor_lab/smartgen/analog/analog_acm_ram_R0C0.mem
电流监控实验/Project/CurrentMonitor_lab/smartgen/analog/analog_assc.mem
电流监控实验/Project/CurrentMonitor_lab/smartgen/analog/analog_assc_ram.hex
电流监控实验/Project/CurrentMonitor_lab/smartgen/analog/analog_assc_ram.v
电流监控实验/Project/CurrentMonitor_lab/smartgen/analog/analog_assc_ram_R0C0.mem
电流监控实验/Project/CurrentMonitor_lab/smartgen/analog/analog_assc_wrapper.v
电流监控实验/Project/CurrentMonitor_lab/smartgen/analog/analog_smev.mem
电流监控实验/Project/CurrentMonitor_lab/smartgen/analog/analog_smev_ram.hex
电流监控实验/Project/CurrentMonitor_lab/smartgen/analog/analog_smev_ram.v
电流监控实验/Project/CurrentMonitor_lab/smartgen/analog/analog_smev_ram_R0C0.mem
电流监控实验/Project/CurrentMonitor_lab/smartgen/analog/analog_smev_wrapper.v
电流监控实验/Project/CurrentMonitor_lab/smartgen/analog/analog_smtr.mem
电流监控实验/Project/CurrentMonitor_lab/smartgen/analog/analog_smtr_ram.hex
电流监控实验/Project/CurrentMonitor_lab/smartgen/analog/analog_smtr_ram.v
电流监控实验/Project/CurrentMonitor_lab/smartgen/analog/analog_smtr_ram_R0C0.mem
电流监控实验/Project/CurrentMonitor_lab/smartgen/analog/analog_smtr_wrapper.v
电流监控实验/Project/CurrentMonitor_lab/smartgen/analog/hdlsynchk.tcl
电流监控实验/Project/CurrentMonitor_lab/smartgen/analog_work.ixf
电流监控实验/Project/CurrentMonitor_lab/smartgen/common/commonFileInventory.xml
电流监控实验/Project/CurrentMonitor_lab/smartgen/common/verilog/assc.v
电流监控实验/Project/CurrentMonitor_lab/smartgen/common/verilog/initcfg.v
电流监控实验/Project/CurrentMonitor_lab/smartgen/common/verilog/initcfg_xa.v
电流监控实验/Project/CurrentMonitor_lab/smartgen/common/verilog/initcfg_xb.v
电流监控实验/Project/CurrentMonitor_lab/smartgen/common/verilog/initcfg_xc.v
电流监控实验/Project/CurrentMonitor_lab/smartgen/common/verilog/initcfg_xd.v
电流监控实验/Project/CurrentMonitor_lab/smartgen/common/verilog/initcfg_xe.v
电流监控实验/Project/CurrentMonitor_lab/smartgen/common/verilog/initcfg_xf.v
电流监控实验/Project/CurrentMonitor_lab/smartgen/common/verilog/smev.v
电流监控实验/Project/CurrentMonitor_lab/smartgen/common/verilog/smtr.v
电流监控实验/Project/CurrentMonitor_lab/smartgen/flashmem/flashmem.cfg
电流监控实验/Project/CurrentMonitor_lab/smartgen/flashmem/flashmem.cxf
电流监控实验/Project/CurrentMonitor_lab/smartgen/flashmem/flashmem.efc
电流监控实验/Project/CurrentMonitor_lab/smartgen/flashmem/flashmem.gen
电流监控实验/Project/CurrentMonitor_lab/smartgen/flashmem/flashmem.log
电流监控实验/Project/CurrentMonitor_lab/smartgen/flashmem/flashmem.mem
电流监控实验/Project/CurrentMonitor_lab/smartgen/flashmem/flashmem.v
电流监控实验/Project/CurrentMonitor_lab/smartgen/flashmem/flashmem_init_wrapper.v
电流监控实验/Project/CurrentMonitor_lab/smartgen/flashmem_work.ixf
电流监控实验/Project/CurrentMonitor_lab/smartgen/PLL1/PLL1.cxf
电流监控实验/Project/CurrentMonitor_lab/smartgen/PLL1/PLL1.gen
电流监控实验/Project/CurrentMonitor_lab/smartgen/PLL1/PLL1.log
电流监控实验/Project/CurrentMonitor_lab/smartgen/PLL1/PLL1.v
电流监控实验/Project/CurrentMonitor_lab/smartgen/PLL1_work.ixf
电流监控实验/Project/CurrentMonitor_lab/smartgen/smartgen.aws
电流监控实验/Project/CurrentMonitor_lab/synthesis/.recordr

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